元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004HIGHĆPERFORMANCE BATTERY MONITOR IC WITH COULOMB COUNTER, VOLTAGE AND, TEMPERATURE MEASUREMENTFEATURESDMultifunction Monitoring Integrated CircuitDESCRIPTIONThe bq26220 is an advanced battery monitoringdevice designed to accurately measure thecharge and discharge currents in rechargeablebattery packs. Intended for pack integration, thebq26220 contains all the necessary functions toform the basis of a comprehensive batterycapacity management system in portableapplications such as cellular phones, PDA’s, orother portable products.The bq26220 works with the host controller in theportable system to implement the batterymanagement system. The host controller isresponsible for interpreting the bq26220 data andcommunicating meaningful battery data to theend-user or power management system.This device provides 64 bytes of general-purposeflash memory, 8 bytes of ID ROM and 32 bytes offlash-backed RAM for data storage. Thenonvolatile memory can maintain formattedbattery monitor information, identification codes,warranty information, or other critical batteryparameters during periods when the battery istemporarily shorted or deeply discharged.DDDDDDDDDDDD Designed to Work With an Intelligent HostController :− Provides State of Charge Information forRechargeable Batteries− Provides Accurate Battery Voltage andTemperature MeasurementHigh Accuracy Coulometric Charge andDischarge Current Integration WithAutomatic Offset Compensation11-Bit Analog-to-Digital Converter ReportsBattery Voltage With Gain and OffsetCorrectionDifferential Current Sense32 Bytes of General Purpose RAM96 Bytes of Flash (Including 32 Bytes ofShadow Flash)8 Bytes of ID ROMInternal Temperature Sensor Eliminates theNeed for an External ThermistorProgrammable Digital Input/Output PortHigh-Accuracy Internal Timebase EliminatesExternal Crystal OscillatorLow Power Consumption:− Operating : 30 µA− Sleep: 1 µA− Hibernate: 600 nASingle-Wire HDQ Serial InterfacePackaging: 8-LEAD TSSOPPW PACKAGE(TOP VIEW)RBIVCCVSSHDQ12348765GPIOSRPSRNBATPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2002, Texas Instruments Incorporatedwww.ti.com1元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004ORDERING INFORMATION{TA−20_C to 70_CPACKAGETSSOPPART NUMBERbq26220PWTOP MARKING26220†PW (TSSOP−8) package is available taped and reeled. Add R suffix to device type (e.g. bq26220PWR) toorder quantities of 2000 devices per reel for TSSOP-8.ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1)bq26220Supply voltage (VCC with respect to GND)Input voltage, SRP and SRN, RBI, GPIO and BAT (all with respect to GND)Input voltage, HDQ (with respect to GND)Output current (GPIO)Output current (HDQ)Operating free-air temperature range, TAStorage temperature range, TstgLead temperature (soldering, 10 s)−0.3 to +7.0−0.3 V to VCC + 0.3 V−0.3 to +7.055−20°C to 70°C− 65°C to 150°C300°CVUNITmA(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,and operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabilityRECOMMENDED OPERATING CONDITIONSPARAMETERVCCV(POR)TASupply voltagePower-on reset voltageOperating ambient temperatureMIN2.81.9−20MAX4.52.4570UNITVV_C2www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220dc electrical characteristics over recommended operating temperature and supply voltage (unlessotherwise noted)PARAMETERICC(OP)I(SLEEP)Supply currentSleep currentTEST CONDITIONSVCC = 4.3 V, flash programming not activeVCC = 4.3 V, flash programming not active0 < VCC < VPORVCC = 5.5VCC = 5.5RBI pin only,VOL = 0.4 V 1.2 V< VCC < V(POR)MINTYP3012121MAX37560030302510.7VCC < 4.2 VVCC > 4.2 V1.71.9100.2 V < (V(SRP) − V(SRN)) < VCC10MΩVUNITµAnAmAnAmAI(HIBERNATE)Hibernate currentICC(PROG)Flash programming supply currentICC(ERASE)Flash erase supply currentI(RBI)Register back-up currentIOLVILVIHRBATRSRDigital output low sink current, GPIOand HDQ pinsDigital input low, GPIO and HDQ pinsDigital input high, GPIO and HDQ pinsBAT input impedanceSRP, SRN input impedancetimer characteristics over recommended operating temperature and supply voltage (unlessotherwise noted)PARAMETERE(TMR)Timer accuracy errorTEST CONDITIONSMIN−4%TYPMAX4%UNITtemperature register characteristics over recommended operating temperature and supplyvoltage (unless otherwise noted)PARAMETERT(RES)E(T)Reported temperature resolutionReported temperatureaccuracyBQ26220PWTSSOP package−4TEST CONDITIONSMINTYP0.254_KMAXUNITvoltage ADC specification, over recommended operating temperature and supply voltage, (unlessotherwise noted)PARAMETERLeast significant bit (LSB)(1)Integral nonlinearity (INL)Differential nonlinearity (DNL)Offset errorMaximum errorTEST CONDITIONS2.6 V ≤ VBAT ≤ 4.5 V2.6 V ≤ VBAT ≤ 4.5 V, Vcc=VBAT2.6 V ≤ VBAT ≤ 4.5 V, Vcc=VBAT2.6 V ≤ VBAT ≤ 4.5 V, Vcc=VBAT2.6 V ≤ VBAT ≤ 4.5 V, Vcc=VBAT−4−1−3−9MINTYP2.44+4+1+14+15MAXUNITmVLSBLSBLSBLSBNOTE 1.For a more detailed explantion of parameters refer to the application note, Understanding Data Converters, TI Literature No. SLAA013.www.ti.com3元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004VFC characteristics over recommended operating temperature and supply voltage (unlessotherwise noted)PARAMETERVI(SR)G(VFC)G(VCC)G(TCO)INLV(COS)Input voltage VSRP − VSRNCharge/discharge gainSupply voltage gain coefficientTemperature gain coefficientIntegrated nonlinearityAuto compensated offset−100 mV < (V(SRP) − V(SRN)) < 100 mV2.8 V ≤ VCC ≤ 4.2 V−20TEST CONDITIONSTemperature = 25 _C, VCC = 3.6−100 mV < (V(SRP) − V(SRN)) < 100 mVMIN−10088910.50.0050.2%−10.5%20µVTYPMAX10094UNITmVHz/V%/V%/_Cflash memory characteristics over recommended operating temperature and supply voltage(unless otherwise noted)PARAMETERData retentionFlash programming write-cyclest(BYTEPROG)Byte programming timeRAM-to-flash block programmingt(BLCKPROG)timet(BLKERASE)Block-erase time10,0009060 µs + 30 µs/byte60 µs + 30 µs/byte10201020µsTEST CONDITIONSMINTYPMAX5UNITYearsCyclesstandard serial communication (HDQ) timing specification over recommended operatingtemperature and supply voltage (unless otherwise noted). See Figures 1 and 2.PARAMETERT(B)T(BR)T(CYCH)T(HW1)T(HW0)T(RSPS)Break timingBreak recoveryHost bit windowHost sends 1Host sends 0bq26220 to host responseTEST CONDITIONSMIN1904019032100190190532805014550145320250nsµsµsTYPMAXUNITT(CYCB)bq26220 bit windowT(start−detect)(1)T(DW1)T(DW0)bq26220, sends 1bq26220, sends 0NOTE 1.The HDQ engine of the bq26220 interpret a 5 ns or longer glitch on HDQ as a bit start. A sufficient number of glitches at 5 ns or longercould result in incorrect data being written to the device. The HDQ line should be properly deglitched to ensure that this does not occur.4www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220PARAMETER MEASUREMENT INFORMATIONT(B)T(BR)T(CYCH)T(HW1)T(HW0)T(CYCB)T(DW1)T(DW0)Figure 1. HDQ Timing DiagramCOMMAND BYTE(Written by Host to bq26220)BREAK0(LSB)1REGISTER ADDRESS234567(MSB)0(LSB)1DATA BYTE(Received by Host From bq26220)234567(MSB)t(RSPS)Figure 2. Typical Communication with the bq26220www.ti.com5元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004FUNCTIONAL BLOCK DIAGRAMTemperatureCompensatedPrecisionOscillatorVCCBandgap,Reference andBiasTimerSystem I/Oand ControlGPIOHDQSRPSRNAutocalibratingVFCRAMUserRegistersRBITemperatureSensorFlashMultiplexerBATVSSIDUDG−02050ADCTERMINAL FUNCTIONSTERMINALNAMEBATRBIGPIOHDQNo.5184I/OIII/OI/ODESCRIPTIONBattery voltage sense input. This pin is used for sensing and measuring the battery voltage.Register backup input. The RBI input pin is used with a storage capacitor or external supply toprovide backup potential to the internal RAM and registers while VCC is < V(POR).General-purpose input/output pin. GPIO is a general-purpose programmable input or output portwhose state is controlled via the HDQ serial communications interface.Single-wire HDQ interface. HDQ is a single-wire serial communications interface port. Thisbidirectional input/output communicates the register information to the host.Current sense input 2. The bq26220 interprets charge and discharge activity by monitoring andintegrating the voltage drop, VSR, across pins SRP and SRN. The SRN input connects to thesense resistor and the negative terminal of the pack. VSRP < VSRN indicates discharge, andVSRP > VSRN indicates charge.Current sense input 1. The bq26220 interprets charge and discharge activity by monitoring andintegrating the voltage drop, VSR, across pins SRP and SRN. The SRP input connects to thesense resistor and the negative terminal of the battery. VSRP < VSRN indicates discharge, andVSRP > VSRN indicates charge.Supply voltageGroundSRN6ISRPVCCVSS723II−6www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220APPLICATION INFORMATIONPACK+C40.1 µFC30.1 µF12Additional ESDProtectionR5R4100 Ω100 ΩHDQD15.6 VProtection ControllerPACK−UDG−04012U1bq26220PWRBIVCCVSSHDQGPIO8SRP7SRN6BAT5C20.1 µFC10.1 µFR3100 kΩR2100 kΩ+34R10.02 ΩFigure 3. Typical Application Circuit for a Single-Cell Li-Ion Applicationfunctional descriptionThe bq26220 measures the voltage drop across a low-value series current-sense resistor between the SRPand SRN pins using a voltage-to-frequency converter. The cell voltage is sensed between the BAT and VSSpins. All data is placed into various internal counter and timer registers. Using information from the bq26220,the system host can determine the battery state-of-charge, estimate self discharge, and calculate the averagecharge and discharge currents. During pack storage periods, the use of an internal temperature sensor doublesthe self-discharge count rate every 10°C above 25°C. The VFC offset is automatically compensated for in thecharge and discharge counter registers.Access to the registers and control of the bq26220 is accomplished through a single-wire interface through aregister mapped command protocol. This protocol includes placing the device in the low-power mode,hardware-register reset, programming flash from RAM, and transferring flash data to RAM.The bq26220 can operate directly from a single Li-Ion cell as long as VCC is between 2.8 V and 4.5 V.www.ti.com7元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004APPLICATION INFORMATIONcharge and discharge count operationTable 1 shows the main counters and registers of the bq26220.The bq26220 accumulates charge and discharge counts into two count registers, the charge count register(CCR) and the discharge count register (DCR). Charge and discharge counts are generated by sensing thevoltage difference between SRP and SRN. The CCR or DCR independently counts, depending on the signalbetween pins SRP and SRN.During discharge, the DCR and the discharge time counter (DTC) are active. If (V(SRP) − V(SRN)) is less than0, (indicating a discharge activity), the DCR counts at a rate equivalent to one count per 3.05 µVH, and the DTCcounts at a rate of 1.138 counts per second (4096 counts = 1 hour). For example, if no rollover of the DTCregister is incipient, a negative 24.42-mV signal produces 8000 DCR counts and 4096 DTC counts each hour.The amount of charge removed from the battery is easily calculated.During charge, the CCR and the charge time counter (CTC) are active. If (V(SRP) − V(SRN)) is greater than 0,(indicating a charge), the CCR counts at a rate equivalent to one count per 3.05 µVH, and the CTC counts ata rate of 1.138 counts per seconds. In this case a 24.42-mV signal produces 8000 CCR counts and 4096 CTCcounts (assuming no rollover) each hour.The DTC and the CTC are 16-bit registers, with roll over beyond FFFFH. If a rollover occurs, the correspondingbit in the MODE register is set, and the counter increments at 1/256 of the normal rate (16 counts per hour).While in normal operation, the internal RAM and flash registers of the bq26220 may be accessed over the HDQpin.For self-discharge calculation, the self-discharge count register (SCR) counts at a rate of one count every hourat a nominal 25°C. The SCR count rate doubles approximately every 10°C up to 60°C. The SCR count rate ishalved every 10°C below 25°C down to 0°C. The value in SCR is useful in estimating the battery self-dischargebased on capacity and storage temperature conditions.Table 4 shows the bq26220 register memory map. The remaining memory can store user-specific informationsuch as chemistry, serial number, and manufacturing date.sleep mode operationThe bq26220 begins low-power operation in response to the host issuing the sleep command. Before enteringthe low-power state, the host processor writes the command to transfer the registers to flash. After the sleepcommand is sent and the charge/discharge activity is less than the value indicated by the WOE bits shown inTable 2, the chip clock is powered down and data acquisitions functions cease except for self-dischargedetection. During device sleep the bq26220 periodically wakes briefly to maintain the self-discharge registers.The bq26220 wakes on either a low-to-high or high-to-low transition on the HDQ pin.Table 3 shows which registers are active during normal operation, sleep, and hibernate.Table 1. bq26220 CountersNAMEDCRCCRSCRDTCCTCDESCRIPTIONDischarge count registerCharge count registerSelf-discharge count registerDischarge time counterCharge time counterRANGE(V(SRP) − V(SRN)) < VSS (Max. =−100 mV) 3.05 µV/LSB(V(SRP) − V(SRN)) > VSS (Max. = 100 mV) 3.05 µV/LSB1 count/hour at 25°C1 count/0.8789 s (default)1 count/225 s if STD is set1 count/0.8789 s (default)1 count/225 s if STC is setRAM SIZE(BITS)16161616168www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220APPLICATION INFORMATIONTable 2. WOE ThresholdsWOE3–1 (HEX)0h1h2h3h4h5h6h7hVWOE (mV)n/a3.5161.7581.1720.8790.7030.5860.502Table 3. Operational StatesMODENormalSleepHibernateSDRNo active registersACTIVE REGISTERSCCR, DCR, CTC, DTC, SDRhibernate mode operationThe bq26220 enters hibernate mode when Vcc drops below the POR threshold, V(POR). In this mode, thebq26220 draws current from the RBI pin to maintain RAM data. The bq26220 exits hibernate mode only whenVcc is raised above the POR threshold.current sense offset calibration and compensationThe bq26220 automatically and continuously compensates for V(SRP) − V(SRN) offset. No host calibration orcompensation is required.gas gauge control registersThe host maintains the charge and discharge and the self-discharge count registers (CCR, CTC, DCR, DTC,and SCR). To facilitate this maintenance, the bq26220 CLR register resets the specific counter or register pairto zero. The host system clears a register by writing the corresponding register bit to 1. When the bq26220completes the reset, the corresponding bit in the CLR register is automatically reset to 0. Clearing the DTC orCTC registers clears the MODE register bits STC/STD and sets the CTC/DTC count rates to the default valueof 1.138 counts per second.device temperature measurementThe bq26220 reports die temperature in units of oK through register pair TMPH−TMPL. Refer to the TMPregister description for more details.www.ti.com9元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004APPLICATION INFORMATIONbattery voltage measurementThe bq26220 senses the battery voltage on the BAT pin and reports it through register pair BATH−BATL. TheBATH (address = 0x72 – bits 0 through 2) and the BATL low-byte register (address = 0x71) contain the resultof ADC conversion on the battery voltage. The voltage is expressed in an 11-bit binary format with an LSB stepsize of 2.44 mV. Bit 2 of BATH register represents the MSB and bit 0 of the BATL represent the LSB. Thefull-scale voltage for this measurement is 5 V and is optimized for direct sensing in single-cell Li-Ion or Li-polapplications (see Figure 3).Note that Bits 3 through 7 of the BATH register store the offset information for the voltage ADC. The mostsignificant bit is the sign-bit followed by 4 bits of offset data.Also note that LSB gain correction factor, in µV, is stored in address 0x79 (byte 1 of the ID ROM) in 2’scomplement. The host is responsible for applying the LSB gain correction factor and offset to the ADCmeasurements.Correct VBAT = VBAT × (2.44 + LSB correction factor) − offsetexample 1: (If real LSB = + 2.45mV and offset = +80 mV)in address 0x79 ⇒ 0000 1010 (in binary) 2’s complementin BATH (0x72) ⇒ 0101 0XXX (in binary) signed magnitudeTo calculate the correct VBAT:LSB correction factor = +10 µV = +0.01 mVoffset = +10 × 8 mV = 80 mVCorrect VBAT (in mV) = VBAT ×(2.44 + 0.01) − 80example 2: (If real LSB = +2.43 mV and offset = −80 mVin address 0x79 ⇒ 1111 0110 (in binary), 2’s complementin BATH (0x72) ⇒ 1101 0XXX (in binary), signed magnitudeTo calculate the correct VBAT:LSB correction factor = −10 µV= −0.01 mVoffset = −10 × 8 mV = −80 mVCorrect VBAT (in mV) = VBAT ×(2.44 − 0.01) − (−80)10www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220APPLICATION INFORMATIONregister interfaceInformation is exchanged between host system and the bq26220 through the data-register interface. SeeTable 4 below. The register set consists of a 122-location address space of 8-bit bytes segmented into••••HDQADDRESS0x78−0x7F0x73−0x770x720x710x700x6F0x6E0x6D0x6C0x6B0x6A0x690x680x670x660x650x640x630x620x610x600x40−0x5F0x20−0x3F0x00−0x1F8 bytes of factory programmed ID ROM32 bytes of flash shadowed RAM64 bytes of general purpose flash18 special function registersTable 4. Memory MapNAMEIDROM−BATHBATLFPAFPDDCRHDCRLCCRHCCRLSCRHSCRLDTCHDTCLCTCHCTCLMODECLRFCMDTEMPHTEMPLFlashFlashRAM/flashBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT08 bytes of factory-programmed ROM and gain correction factor for BATH and BATLReservedBV−SIGNBVOS3BVOS2BVOS1BVOS0Battery voltage (bits 8 through 10)Battery voltage (bits 0 through 7)Flash program address byteFlash program data byteDischarge count register-high byteDischarge count register-low byteCharge count register-high byteCharge count register-low byteSelf-discharge count register-high byteSelf−discharge count register-low byteDischarge timer counter register-high byteDischarge timer count register-low byteCharge timer counter register-high byteCharge timer counter register-low byteGPIENRSVDSTATRSVDSTCRSVDSTDCTCWOE2DTCWOE1SCRWOE0CCRPORDCRFlash/control command registerTemperature-high byte (bits 0 through 2 only, other bits are reserved)Temperature-low bytePage 2, 32 bytes of flashPage 1, 32 bytes of flashPage 0, 32 bytes of flash shadowed RAMwww.ti.com11元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004APPLICATION INFORMATIONmemoryID ROMLocations 0x7F through 0x78 contain the factory programmed ID ROM and also the LSB gain correction factorfor the voltage analog to digital converter. The format for this register is described in Table 5.Table 5. ID ROM Command Code SummaryBYTE76543210RAM LOCATION0x7F0x7E0x7D0x7C0x7B0x7A0x790x78INFORMATIONDevice code 0x220x00RandomRandomRandomRandomGain correction factorRandomNOTE:For additional information please contact Texas Instruments.flash-shadowed RAMThe host system has direct access to read and modify 32 bytes of RAM. These 32 bytes are shadowed by 32bytes of flash to provide nonvolatile storage of battery conditions. The information stored in RAM is transferredto flash, and the information stored in flash is transferred to RAM by writing a single command into the flashcommand register (FCMD). When a power-on-reset occurs, page 0 of flash is transferred to RAM. For moredetails, refer to the flash command register section.user-flash memoryIn addition to the flash-shadowed RAM, the bq26220 has 64 bytes of user-flash. The user-flash can storespecific battery pack parameters, such as charge per VFC pulse, battery chemistry, and self-discharge rates.flash programmingThe two banks of direct user-flash are programmed one byte at a time, but the single bank of flash-shadowedRAM can be programmed one page at a time or by writing the RAM-to-flash transfer code into the flashcommand register (FCMD). This programming is performed by writing the desired code into the flash commandregister, FCMD (address 0x62), the host may transfer data between flash and RAM, page erase the flash orplace the device into the low power mode. For more details, refer to the flash command register section.Summaries of the flash command codes are shown in Table 6.Table 6. Flash Command Code SummaryCOMMAND CODE(HEX)0x0F0x400x410x420x450x480xF6Program byteErase page 0 flashErase page 1 flashErase page 2 flashTransfer page 0 RAM to page 0 flashTransfer page 0 flash to page 0 RAMPower downDESCRIPTION12www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220APPLICATION INFORMATIONsingle-byte programmingTo program an individual byte in flash, the byte of data is first written into the FPD register while the addressto be programmed is written into the FPA register. The program byte command, 0x0F, is then written to theFCMD. The result of this sequence is that the contents of the FPD register is logically ANDed with the contentsof the flash address pointed to by the FPA register.RAM-to-flash transferThe content of the flash that shadows the user RAM is logically ANDed to the RAM contents when theRAM-to-flash transfer command is sent. If new data is to be written over old data, then it is necessary to firsterase the flash page that is being updated and restore all necessary data.communicating with the bq26220The bq26220 includes a single-wire HDQ serial data interface. Host processors, configured for either polled orinterrupt processing, use the interface to access various bq26220 registers. The HDQ pin requires an externalpull-up resistor. The interface uses a command-based protocol, where the host processor sends a commandbyte to the bq26220. The command directs the bq26220 either to store the next eight bits of data received toa register specified by the command byte, or, to output the eight bits of data from a register specified by thecommand byte.The communication protocol is asynchronous return-to-one and is referenced to VSS. Command and databytes consist of a stream of eight bits that have a maximum transmission rate of 5 Kbits/s. The least-significantbit of a command or data byte is transmitted first. Data input from the bq26220 may be sampled using thepulse-width capture timers available on some microcontrollers. A UART, (universal asynchronous receivertransmitter), also communicates with the bq26220.If a communication time out occurs (for example, if the host waits longer than t(CYCB) for the bq26220 to respondor if this is the first access command), then a BREAK should be sent by the host. The host may then resendthe command. The bq26220 detects a BREAK when the HDQ pin is driven to a logic-low state for a time t(B)or greater. The HDQ pin then returns to its normal ready-high logic state for a time t(BR).The bq26220 is thenready for a command from the host processor.The return-to-one data-bit frame consists of three distinct sections:1.The first section starts the transmission by either the host or the bq26220 taking the HDQ pin to a logic-lowstate for a period equal to t(HW1) or t(DW1).2.The next section is the actual data transmission, where the data should be valid by a period equal to t(HW1)or t(DW1), after the negative edge that starts communication. The data should be held for t(HW0) and t(DW0)periods to allow the host or bq26220 to sample the data bit.3.The final section stops the transmission by returning the HDQ pin to a logic-high state by at least a periodequal to t(DW0) or t(HW0) after the negative edge used to start communication. The final logic-high stateshould be held until a period equal to t(CYCH) or t(CYCB), to allow time to ensure that the bit transmissionceased properly.www.ti.com13元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004APPLICATION INFORMATIONThe serial communication timing specification and illustration sections give the timings for data and breakcommunication. Communication with the bq26220 always occurs with the least significant bit being transmittedfirst. Figure 4 shows an example of a communication sequence to read the bq26220 DCRH register.COMMAND BYTE(Written by Host to bq26220)BREAK0(LSB)12CMDR=6Eh34567(MSB)0(LSB)1DATA BYTE (DCRH) = 64h(Received by Host From bq26220)234567(MSB)0MSBLSB6Eh=0 1 1 0 1 1 1 0111011000100110MSBLSB64h=0 1 1 0 0 1 0 0Figure 4. bq26220 Communication Sequencecommand byteThe command byte of the bq26220 consists of eight contiguous valid command bits. The command bytecontains two fields: W/R Command and address. The W/R bit of the command register determines whether thecommand is a read or a write command while the address field containing bit AD6−AD0 indicates the addressto be read or written. The command byte values are shown in Table 7.Table 7. Command Byte ValuesCOMMAND BYTE7W/R6AD65AD54AD43AD32AD21AD10AD0Table 8. Command Byte DefinitionsIndicates whether the command byte is a read or write command. A 1 indicates a write command and that thefollowing eight bits should be written to the register specified by the address field of the command byte, while a0 indicates that the command is a read. On a read command, the bq26220 outputs the requested registercontents specified by the address field portion of the command byte.The seven bits labeled AD6−AD0 containing the address portion of the register to be accessed.W/RAD6−AD0bq26220 registersregister maintenanceThe host system is responsible for register maintenance. (See Table 4.) To facilitate this maintenance, thebq26220 clear register (CLR) resets the specific counter or register pair to zero. The host system clears aregister by writing the corresponding register bit to 1. When the bq26220 completes the reset, the correspondingbit in the CLR register automatically resets to 0, saving the host an extra write/read cycle. Clearing the DTCregister clears the STD bit and sets the DTC count rate to the default value of one count per 0.8789 s. Clearingthe CTC register clears the STC bit and sets the CTC count rate to the default value of one count per 0.8789 s.14www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220APPLICATION INFORMATIONregister descriptionsbattery voltage offset registers (BATH)Bits 3 through 7 of the BATH register (address = 0x72) store the offset information for the voltage ADC. The mostsignificant bit is the sign bit followed by 4 bits of offset data. Each count of offset represents 8 mV. The host isresponsible for subtracting the offset for the measurement from the uncorrected value found in BATH and BATLregisters. This is a signed magnitude number with Bit 7 being the sign bit. A 1 in Bit 7 means that the numberis negative.battery voltage registers (BATH/BATL)The BATH (address = 0x72 – bits 0 through 2) and the BATL low-byte register (address = 0x71) contain the resultof ADC conversion on the battery voltage. The voltage is expressed in an 11-bit binary format with an LSB stepsize of 2.44 mV. Bit 3 of BATH register represents the MSB and bit 0 of the BATL represent the LSB.flash program address register (FPA)The FPA byte register (address = 0x70) points to the flash address location that is programmed when theprogram flash command is issued. This byte is used with the FPD and FCMD register to program an individualbyte in flash memory.flash program data register (FPD)The FPD byte register (address = 0x6F) contains the data to be programmed into the flash address locationpointed to by the contents of the FPA register. When the program flash command is issued, the contents of theFPD register are ANDed with the contents of the byte pointed to by the FPA and then stored into that location.discharge count registers (DCRH/DCRL)The DCRH high-byte register (address = 0x6E) and the DCRL low-byte register (address = 0x6D) contain thecount of the discharge, and are incremented whenever VSR < VSS These registers continue to count beyondFFFFH, so proper register maintenance by the host system is necessary. The CLR register forces the reset ofboth the DCRH and DCRL to zero.charge count registers (CCRH/CCRL)The CCRH high-byte register (address = 0x6C) and the CCRL low-byte register (address = 0x6B) contain thecount of the charge, and are incremented whenever VSR > VSS. These registers continue to count beyondFFFFH, so proper register maintenance should be done by the host system. The CLR register forces the resetof both the CCRH and CCRL to zero.self-discharge count registers (SCRH/SCRL)The SCRH high-byte register (address = 0x6A) and the SCRL low-byte register (address = 0x69) contain theself-discharge count. This register is continually updated in both the normal operating and sleep modes of thebq26220. The counts in these registers are incremented based on time and temperature. The SCR counts ata rate of one count per hour at 20°C to 30°C. The count rate doubles every 10°C up to a maximum of 16counts/hour at temperatures above 60°C. The count rate halves every 10°C below 20°C to 30°C to a minimumof one count/8 hours at temperature below 0°C. These registers continue to count beyond FFFFH, so properregister maintenance should be done by the host system. The CLR register forces the reset of both the SCRHand SCRL to zero. During device sleep the bq26220 periodically wake for a brief amount of time to maintainthe self-discharge registers.www.ti.com15元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004APPLICATION INFORMATIONdischarge time count registers (DTCH/DTCL)The DTCH high-byte register (address = 0x68) and the DTCL low-byte register (address = 0x67) determine thelength of time the VSR < VSS indicating a discharge. The counts in these registers are incremented at a rate of4096 counts per hour. If the DTCH/DTCL register continues to count beyond FFFFH, the STD bit is set in theMODE/WOE register, indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.Note: If a second rollover occurs, STD is cleared. Access to the bq26220 should be timed to clear DTCH/DTCLmore often than every 170 days. The CLR register forces the reset of both the DTCH and DTCL to zero.charge-time count registers (CTCH/CTCL)The CTCH high-byte register (address = 0x66) and the CTCL low-byte register (address = 0x65) determine thelength of time the VSR >VSS, indicating a charge activity. The counts in these registers are incremented at a rateof 4096 counts per hour. If the CTCH/CTCL registers continue to count beyond FFFFH, the STC bit is set in theMODE/WOE register indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.Note: If a second rollover occurs, STC is cleared. Access to the bq26220 should be timed to clear CTCH/CTCLmore often than every 170 days. The CLR register forces the reset of both the CTCH and CTCL to zero.mode register (MODE)The MODE register (address 0x64) contains the GPIEN, STAT, STC, STD, POR and wake-up enableinformation as described in Table 9.Table 9. MODE Register ValuesMODE BITS7(MSB)GPIENSTATSTCSTDWOE2WOE1WOE06543210(LSB)PORTable 10. MODE Register DefinitionsGPIENSTATSTC & STDGPIEN bit (bit 7) sets the state of the GPIO pin. A 1 configures the GPIO pin as input, while a 0 configures theGPIO pin as open-drain output. This bit is set to 0 on power-on-reset.STAT bit (bit 6) sets the state of the open drain output of the GPIO pin (when configured as output by bit 7). A 1turns off the open drain output while a 0 turns the output on. This bit is set to 1 on power-on-reset.The slow time charge (STC) and slow time discharge (STD) flags indicate if the CTC or DTC registers haverolled over beyond FFFFH. STC set to 1 indicates a CTC rollover; STD set to 1 indicates a DTC rollover.The wake-up output enable (WOE) bits (bits 3, 2 and 1) indicate the voltage level required between SRP andSRN so that the bq26220 enters sleep mode after a power down command is issued. Whenever |VSRP − VSRN|< VWOE, the bq26220 enters sleep mode after the power down command has been issued. On bq26220power-on-reset these bits are set to 1. Setting all of these bits to zero is valid, but result in immediate sleep.Refer to Table 3 for the various WOE values.POR bit (bit 0) indicates a power-on-reset has occurred. This bit is set when VCC has gone below the PORlevel. This bit can be also set and cleared by the host, but has no functionality if set by host.WOE[2.0]POR16www.ti.com元器件交易网www.cecb2b.comSLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004bq26220APPLICATION INFORMATIONclear register (CLR)The bits in the CLR register (address 0x63) clear the DCR, CCR, SCR, DTC, and CTC registers, reset thebq26220 by forcing a power-on-reset and setting the state of the STAT pin as described in Table 11.Table 11. CLR RegisterCLR BITS7(MSB)RSVDRSVDRSVDCTCDTCSCRCCR6543210(LSB)DCRTable 12. CLR Register DefinitionsRSVDCTCDTCSCRCCRDCRRSVD bits (bits 5, 6 and 7) are reserved for future use and should be written to 0 by the host.CTC bit (bit 4) clears the CTCH and CTCL registers and the STC bit. A 1 clears the corresponding registers andbit. After the registers are cleared, the CTC bit is cleared. This bit is cleared on power-on-reset.DTC bit (bit 3) clears the DTCH and DTCL registers and the STD bit. A 1 clears the corresponding registers andbit. After the registers are cleared, the DTC bit is cleared. This bit is cleared on power-on-reset.SCR bit (bit 2) clears both the SCRH and SCRL registers. Writing a 1 to this bit clears the SCRH and SCRLregister. After these registers are cleared, the SCR bit is cleared. This bit is cleared on power-on-reset.CCR bit (bit 1) clears both the CCRH and CCRL registers. Writing a 1 to this bit clears the CCRH and CCRLregisters. After these registers are cleared, the CCR bit is cleared. This bit is cleared on power-on-reset.DCR bit (bit 0) clears both the DCRH and DCRL registers. Writing a 1 to this bit clears the DCRH and DCRLregisters. After these registers are cleared, the DCR bit is cleared. This bit is cleared on power-on-reset.flash command register (FCMD)The FCMD register (address 0x62) is the flash command register and programs a single flash byte-location,perform flash page erase, transfer RAM to flash and flash to RAM, enter sleep mode, and power-down. Thesefunctions are performed by writing the desired command code to the FCMD register. After the bq26220 hasfinished executing the issued command, the flash command register is cleared.Table 13. FCMD Register Definitions0x0F0x400x410x420x450x480xF6Program byte command code. This code ANDs the contents of the FPD register with the contents of flash bytelocation pointed to by the contents of the FPA register.Erase page 0 command code. This code erases all the bytes of flash from address 0x00 to 0x1F.Erase page 1 command code. This code erases all the bytes of flash from address 0x20 to 0x3F.Erase page 2 command code. This code erases all the bytes of flash from address 0x40 to 0x5F.RAM-to-flash transfer code. This code programs the contents of the RAM into Page 0 flash, addresses 0x00though 0x1F.Flash-to-RAM transfer code. This code copies the contents of the page 0 flash into RAM.Power-down code. This code places the bq26220 into the sleep mode when the conditions are met as indicatedby the WOE bits in the MODE/WOE register. The part remains in sleep mode until a high-to-low or low-to-hightransition occurs on the HDQ pin.www.ti.com17元器件交易网www.cecb2b.combq26220SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004APPLICATION INFORMATIONtemperature registers (TMPH, TMPL)The TMPH (address 0x61) and the TMPL registers (address 0x60) reports die temperature in hex format in unitsof 0.25_K.The temperature is reported as 11 bits of data, using all 8 bits of the TMPL low register and the 3 bitsof the TMPH register. The temperature should be read as the concatenation of TMPH [2:0] and TMPL [7:0],0.25_K/LSB. The 5 MSBs of TMPH, TMPH [7:3], are cleared on POR and are reserved. The 5 bits should alsobe masked off when reading the temperature, to ensure that incorrect data is not used when calculating thetemperature.18www.ti.com元器件交易网www.cecb2b.com
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