Revised September 2000
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous statechanges are initiated by the falling edge of the clock. Trig-gering occurs at a voltage level of the clock and is notdirectly related to the transition time. The J and K inputscan change when the clock is in either state without affect-ing the flip-flop, provided that they are in the desired stateduring the recommended setup and hold times relative tothe falling edge of the clock. A LOW signal on SD or CDprevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q andQ HIGH.Asynchronous Inputs:
LOW input to SD sets Q to HIGH levelLOW input to CD sets Q to LOW levelClear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Qand Q HIGH
Ordering Code:
Order Number Package Number74F112SC 74F112SJ 74F112PC
M16AM16DN16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic SymbolsConnection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor CorporationDS009472www.fairchildsemi.com
74F112Unit Loading/Fan Out
Pin NamesJ1, J2, K1, K2CP1, CP2CD1, CD2SD1, SD2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)Direct Clear Inputs (Active LOW)Direct Set Inputs (Active LOW)
Description
U.L.
Input IIH/IIL
HIGH/LOWOutput IOH/IOL1.0/1.01.0/4.01.0/5.01.0/5.050/33.3
20 µA/−0.6 mA20 µA/−2.4 mA20 µA/−3.0 mA20 µA/−3.0 mA
Q1, Q2, Q1, Q2Outputs
−1 mA/20 mA
Truth Table
Inputs
SDLHLHHHH
CDHLLHHHH
CPXXX
JXXXhlhl
KXXXhhll
OutputsQHLHQ0LHQ0
QLHHQ0HLQ0
H (h) = HIGH Voltage LevelL (l) = LOW Voltage LevelX = Immaterial
= HIGH-to-LOW Clock Transition
Q0(Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com2
74F112Absolute Maximum Ratings(Note 1)
Storage Temperature
Ambient Temperature under BiasJunction Temperature under BiasVCC Pin Potential to Ground PinInput Voltage (Note 2)Input Current (Note 2)Voltage Applied to Outputin HIGH State (with VCC = 0V)Standard Output3-STATE OutputCurrent Applied to Outputin LOW State (Max)
twice the rated IOL (mA)
−65°C to +150°C−55°C to +125°C−55°C to +150°C−0.5V to +7.0V−0.5V to +7.0V−30 mA to +5.0 mA
Recommended OperatingConditions
Free Air Ambient TemperatureSupply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to VCC−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the devicemay be damaged or have its useful life impaired. Functional operationunder these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
SymbolVIHVILVCDVOHVOLIIHIBVIICEXVIDIODIIL
Parameter
Input HIGH VoltageInput LOW VoltageInput Clamp Diode VoltageOutput HIGHVoltageOutput LOWVoltageInput HIGHCurrent
Input HIGH CurrentBreakdown TestOutput HIGHLeakage CurrentInput LeakageTest
Output LeakageCircuit CurrentInput LOW Current
4.75
3.75−0.6−2.4−3.0
IOSICCHICCL
Output Short-Circuit CurrentPower Supply CurrentPower Supply Current
−60
1212
−1501919
mAmAmA
MaxMaxMax
mA
Max
10% VCC 5% VCC10% VCC
2.52.7
0.55.07.050
VµAµAµAVµA
MinMaxMaxMax0.00.0
Min2.0
0.8−1.2
Typ
Max
UnitsVVVV
MinMinVCC
Conditions
Recognized as a HIGH SignalRecognized as a LOW SignalIIN = −18 mAIOH = −1 mAIOH = −1 mAIOL = 20 mAVIN = 2.7VVIN = 7.0VVOUT = VCCIID = 1.9 µA
All other pins groundedVIOD = 150 mVAll other pins groundedVIN = 0.5V (Jn, Kn)VIN = 0.5V (CPn)VIN = 0.5V (CDn, SDn)VOUT = 0VVO = HIGHVO = LOW
3www.fairchildsemi.com
74F112AC Electrical Characteristics
TA = +25°C
Symbol
Parameter
Min
fMAXtPLHtPHLtPLHtPHL
Maximum Clock FrequencyPropagation DelayCPn to Qn or QnPropagation DelayCDn, SDn to Qn, Qn
852.02.02.02.0
VCC = +5.0VCL = 50 pF
Typ1055.05.04.54.5
6.56.56.56.5Max
TA = 0°C to +70°CVCC = +5.0VCL = 50 pFMin802.02.02.02.0
7.57.57.57.5Max
MHznsnsUnits
AC Operating Requirements
TA = +25°C
SymboltS(H)tS(L)tH(H)tH(L)tW(H)tW(L)tW(L)tREC
Setup Time, HIGH or LOWJn or Kn to CPn
Hold Time, HIGH or LOWJn or Kn to CPnCP Pulse WidthHIGH or LOWPulse Width, LOWCDn or SDnRecovery TimeSDn, CDn to CP
Parameter
VCC = +5.0VMin4.03.0004.54.54.54.0
Max
TA = 0°C to +70°CVCC = +5.0VMin5.03.5005.05.05.05.0
nsnsnsns
Max
Units
www.fairchildsemi.com4
74F112Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5www.fairchildsemi.com
74F112Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
www.fairchildsemi.com6
74F112 Dual JK Negative Edge-Triggered Flip-FlopPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.
7
2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
因篇幅问题不能全部显示，请点此查看更多更全内容