USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY anther_mini_MCU IS
PORT( anther_signal_in:in std_logic;
anther_MCU_RST:IN STD_LOGIC;
anther_led_signal_output:out std_logic_vector(2 downto 0) ); END ;
ARCHITECTURE one OF anther_mini_MCU IS BEGIN PROCESS(anther_signal_in)
VARIABLE timer: STD_LOGIC_VECTOR(1DOWNTO 0):=\"00\";
VARIABLE current_state,next_state: STD_LOGIC_VECTOR(2DOWNTO 0):=\"100\"; begin
IF anther_MCU_RST='1' THEN
IF anther_signal_in'EVENT AND anther_signal_in='1' THEN IF timer=\"10\" THEN timer:=\"00\"; ELSE timer:=timer+1; end if; END IF; end if;
IF anther_MCU_RST='0' THEN timer:=\"00\";
END IF; CASE timer IS
WHEN \"00\"=> current_state:=next_state; next_state:=\"100\"; WHEN \"01\"=> current_state:=next_state; next_state:=\"010\"; WHEN \"10\"=> current_state:=next_state; next_state:=\"001\"; WHEN OTHERS => NULL; end case;
anther_led_signal_output<=current_state; end process; end ;
cnt24部分： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt24 IS
PORT(CLK24,RST24:IN STD_LOGIC;
OUT24:OUT STD_LOGIC_VECTOR(4 DOWNTO 0); COUT24:OUT STD_LOGIC); END;
ARCHITECTURE one OF cnt24 IS BEGIN
PROCESS(CLK24,RST24)
VARIABLE Q: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN
IF RST24='0' THEN Q:=(OTHERS=>'0');
ELSIF CLK24'EVENT AND CLK24='1' THEN IF Q<23 THEN Q:=Q+1; ELSE Q:=(OTHERS=>'0'); END IF; END IF;
IF Q=\"10111\" THEN COUT24<='1'; ELSE COUT24<='0'; END IF; OUT24<=Q; END PROCESS; END;
cnt60部分 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt60 IS
PORT(CLK60,RST60:IN STD_LOGIC;
OUT60:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); COUT60:OUT STD_LOGIC); END;
ARCHITECTURE one OF cnt60 IS BEGIN
PROCESS(CLK60,RST60)
VARIABLE Q: STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN
IF RST60='0' THEN Q:=(OTHERS=>'0');
ELSIF CLK60'EVENT AND CLK60='1' THEN IF Q<59 THEN Q:=Q+1; ELSE Q:=(OTHERS=>'0'); END IF; END IF;
IF Q=\"1001011\" THEN COUT60<='1'; ELSE COUT60<='0'; END IF; OUT60<=Q; END PROCESS; END;
Counter部分 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter IS
PORT( CH:IN STD_LOGIC_VECTOR(2 DOWNTO 0); second_in,RST_couter,all_RST:IN STD_LOGIC;
led_signal_output:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
YELLOW_SIGNAL,GREEN_SIGNAL,RED_SIGNAL,signal_output:OUT STD_LOGIC); END;
ARCHITECTURE one OF counter IS BEGIN
PROCESS(second_in,RST_couter)
VARIABLE Q: STD_LOGIC_VECTOR(5 DOWNTO 0):=\"000000\"; --VARIABLE XX: STD_LOGIC_VECTOR(2 DOWNTO 0):=\"100\";
BEGIN
IF all_RST='1' THEN
IF RST_couter='1' THEN
IF second_in'EVENT AND second_in='1' THEN CASE CH IS
WHEN \"100\" => IF Q>33 THEN
Q:=\"000000\"; signal_output<='1'; ELSE Q:=Q+1; signal_output<='0'; END IF;
WHEN \"010\" => IF Q>3 THEN Q:=\"000000\"; signal_output<='1'; ELSE Q:=Q+1; signal_output<='0' ;END IF;
WHEN \"001\" => IF Q>38 THEN
Q:=\"000000\"; signal_output<='1'; ELSE Q:=Q+1; signal_output<='0'; END IF;
WHEN OTHERS => NULL; END CASE; END IF; END IF; END IF;
IF all_RST='0' THEN Q:=\"000000\"; END IF;
IF RST_couter='0' OR all_RST='0' THEN RED_SIGNAL <= '1'; YELLOW_SIGNAL <='0';GREEN_SIGNAL <='0';-- RST '0' ELSE
CASE CH IS
WHEN \"100\" => RED_SIGNAL <= '1'; YELLOW_SIGNAL <='0';GREEN_SIGNAL <='0'; WHEN \"010\" => RED_SIGNAL <= '0'; YELLOW_SIGNAL <='1';GREEN_SIGNAL <='0'; WHEN \"001\" => RED_SIGNAL <= '0'; YELLOW_SIGNAL <='0';GREEN_SIGNAL <='1'; WHEN OTHERS => RED_SIGNAL <= '0'; YELLOW_SIGNAL <='0';GREEN_SIGNAL <='0' ; END CASE; END IF;
led_signal_output<=Q; END PROCESS; END;
frequency divider部分 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY frequency_divider IS
PORT(frequency_in:IN STD_LOGIC; frequency_en:IN STD_LOGIC;
frequency_out0,frequency_out1,frequency_out2:OUT STD_LOGIC); END;
ARCHITECTURE one OF frequency_divider IS BEGIN
PROCESS(frequency_in)
VARIABLE B:INTEGER RANGE 0 TO 999 ; VARIABLE A:STD_LOGIC; BEGIN
IF frequency_en='1' THEN
IF frequency_in'EVENT AND frequency_in='1' THEN B:=B+1;
IF B=999 THEN B:=0;
IF A='1' THEN A:='0'; ELSE A:='1'; END IF; END IF; END IF; END IF;
frequency_out0<=A; frequency_out1<=A; frequency_out2<=A; END PROCESS; END;
LED部分： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY led IS
PORT( led_in:in std_logic_vector(5 downto 0); led_RST,led_CLK:in std_logic;
led_shi_out:out std_logic_vector(6 downto 0); led_ge_out:out std_logic_vector(6 downto 0));
END ;
ARCHITECTURE one OF led IS
SIGNAL GGE:std_logic_vector(5 downto 0); BEGIN
PROCESS(led_in)
VARIABLE C:std_logic_vector(5 downto 0); VARIABLE GE:std_logic_vector(5 downto 0); VARIABLE NUM:std_logic_vector(5 downto 0); begin C:=led_in; NUM:=C;
IF NUM>9 THEN
NUM:=NUM-10; ELSE GE:=NUM; END IF;
IF NUM>9 THEN NUM:=NUM-10; ELSE GE:=NUM; END IF;
IF NUM>9 THEN NUM:=NUM-10; ELSE GE:=NUM; END IF;
IF NUM>9 THEN NUM:=NUM-10; ELSE GE:=NUM; END IF; IF NUM>9 THEN NUM:=NUM-10; GE:=NUM; ELSE GE:=NUM; END IF; GGE<=GE; END PROCESS;
PROCESS (GGE,led_in,led_CLK,led_RST)
VARIABLE SHI:std_logic_vector(5 downto 0);
VARIABLE DATA_IN:std_logic_vector(5 downto 0); VARIABLE DATA:std_logic_vector(3 downto 0); VARIABLE ENA:STD_LOGIC:='1'; BEGIN
DATA_IN:=led_in;
IF DATA_IN=GGE THEN SHI:=\"000000\";
ELSE SHI:=DATA_IN-GGE; END IF;
IF ENA='1' THEN CASE GGE IS
WHEN \"000000\"=> led_ge_out<=\"0111111\";--0 3F WHEN \"000001\"=> led_ge_out<=\"0000110\";--1 06 WHEN \"000010\"=> led_ge_out<=\"1011011\";--2 5B WHEN \"000011\"=> led_ge_out<=\"1001111\";--3 4F WHEN \"000100\"=> led_ge_out<=\"1100110\";--4 66 WHEN \"000101\"=> led_ge_out<=\"1101101\";--5 6D WHEN \"000110\"=> led_ge_out<=\"1111101\";--6 7D WHEN \"000111\"=> led_ge_out<=\"0000111\";--7 07 WHEN \"001000\"=> led_ge_out<=\"1111111\";--8 7F WHEN \"001001\"=> led_ge_out<=\"1101111\";--9 6F WHEN OTHERS=> NULL; end case; CASE SHI IS
WHEN \"000000\"=> led_shi_out<=\"0111111\"; WHEN \"001010\"=> led_shi_out<=\"0000110\"; WHEN \"010100\"=> led_shi_out<=\"1011011\"; WHEN \"011110\"=> led_shi_out<=\"1001111\"; WHEN \"101000\"=> led_shi_out<=\"1100110\"; WHEN \"110010\"=> led_shi_out<=\"1101101\"; WHEN OTHERS=> NULL; end case;
ELSE led_shi_out<=\"0000000\";led_ge_out<=\"0000000\"; END IF;
if led_RST='0' then
IF led_CLK'EVENT AND led_CLK='1' THEN DATA:=DATA+1;
IF DATA=\"0011\" THEN ENA:='0';DATA:=\"0000\"; ELSE ENA:='1'; END IF; END IF; END IF;
IF led_RST='1' then ENA:='1'; END IF; end process; end;
mini_MCU部分 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mini_MCU IS
PORT( signal_in:in std_logic;
MCU_RST:IN STD_LOGIC;
led_signal_output:out std_logic_vector(2 downto 0) ); END ;
ARCHITECTURE one OF mini_MCU IS BEGIN PROCESS(signal_in)
VARIABLE timer: STD_LOGIC_VECTOR(1DOWNTO 0):=\"00\";
VARIABLE current_state,next_state: STD_LOGIC_VECTOR(2DOWNTO 0):=\"100\"; begin
IF MCU_RST='1' THEN
IF signal_in'EVENT AND signal_in='1' THEN IF timer=\"10\" THEN timer:=\"00\"; ELSE timer:=timer+1; end if; END IF; end if;
IF MCU_RST='0' THEN timer:=\"00\";
end if; CASE timer IS
WHEN \"00\"=> current_state:=next_state; next_state:=\"001\"; WHEN \"01\"=> current_state:=next_state; next_state:=\"100\"; WHEN \"10\"=> current_state:=next_state; next_state:=\"010\"; WHEN OTHERS => NULL; end case;
led_signal_output<=current_state; end process; end ;
traffic_light部分
把上面的部分汇总加到一起就能用了
因篇幅问题不能全部显示，请点此查看更多更全内容