LTC2226H12-Bit, 25Msps125°C ADC in LQFPFEATURES
n n n n n n n n n n n nDESCRIPTION
The LTC®2226H is a 12-bit 25Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2226H is perfect for demanding imaging and communications applications with AC performance that includes 71.4dB SNR and 90dB SFDR.DC specs include ±0.3LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS.A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic.A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles., LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.Sample Rate: 25Msps–40°C to 125°C OperationSingle 3V Supply (2.8V to 3.5V)Low Power: 75mW71.4dB SNR90dB SFDRNo Missing CodesFlexible Input: 1VP-P to 2VP-P Range575MHz Full Power Bandwidth S/HClock Duty Cycle StabilizerShutdown and Nap ModesPin Compatible Familyn LTC2246H (14-Bit), LTC2226H (12-Bit)n 48-Pin (7mm × 7mm) LQFP PackageAPPLICATIONS
Automotiven Industrialn Wireless and Wired Broadband CommunicationnTYPICAL APPLICATION
Typical INL, 2V Range1.00
REFHREFL
FLEXIBLEREFERENCEINL ERROR (LSB)OVDD
0.750.500.250–0.25–0.50–0.75
CLOCK/DUTYCYCLECONTROLCLK2226 TA01+ANALOGINPUT–INPUTS/H12-BITPIPELINEDADC CORECORRECTIONLOGICOUTPUTDRIVERSD11•••D0OGND–1.00
01024
2048CODE
30724096
2226 TA01b
2226hfb1
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LTC2226HABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)PIN CONFIGURATION
TOP VIEW
GNDVDDVDDVCMVCMSENSEMODEOFD11D10D9GNDGND1AIN+2AIN–3GND4REFH5REFH6REFL7REFL8GND9VDD10VDD11VDD12
484746454443424140393837Supply Voltage (VDD) ..................................................4VDigital Output Ground Voltage (OGND) ........–0.3V to 1VAnalog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)Digital Input Voltage ......................–0.3V to (VDD + 0.3V)Digital Output Voltage ................–0.3V to (OVDD + 0.3V)Power Dissipation .............................................1500mWOperating Temperature Range................–40°C to 125°CStorage Temperature Range ...................–65°C to 150°C36
3534333231302928272625GNDD8D7D6GNDOVDDOGNDGNDD5D4D3GND
LX PACKAGE
48-LEAD (7mm s 7mm) PLASTIC LQFP
TJMAX = 150°C, θJA = 53°C/WORDER INFORMATION
LEAD FREE FINISHLTC2226HLX#PBFLEAD BASED FINISHLTC2226HLXTAPE AND REELLTC2226HLX#TRPBFTAPE AND REELLTC2226HLX#TRPART MARKINGLTC2226LXPART MARKINGLTC2226LXPACKAGE DESCRIPTION48-Lead (7mm × 7mm) Plastic LQFPPACKAGE DESCRIPTION48-Lead (7mm × 7mm) Plastic LQFPTEMPERATURE RANGE–40°C to 125°CTEMPERATURE RANGE–40°C to 125°CConsult LTC Marketing for parts specifi ed with wider operating temperature ranges.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/CONVERTER CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)PARAMETERResolution (No Missing Codes)Integral Linearity ErrorDifferential Linearity ErrorOffset ErrorGain ErrorOffset DriftFull-Scale DriftTransition NoiseInternal ReferenceExternal ReferenceSENSE = 1VDifferential Analog Input (Note 5)Differential Analog Input(Note 6)External ReferenceCONDITIONSlllllGND13CLK14GND15SHDN16OE17GND18NC19NC20D021D122D223GND24MIN12–1.5–0.8–15–3TYP±0.3±0.15±2±0.5±10±30±50.25MAX1.50.8153UNITSBitsLSBLSBmV%FSμV/°Cppm/°Cppm/°CLSBRMS2226hfb2
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LTC2226HANALOG INPUT The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)PARAMETERAnalog Input Range (AIN+ – AIN–)Analog Input Common Mode (AIN+ + AIN–)/2Analog Input Leakage CurrentSENSE Input LeakageMODE Pin LeakageSample-and-Hold Acquisition Delay TimeSample-and-Hold Acquisition Delay Time JitterAnalog Input Common Mode Rejection RatioSYMBOLVINVIN, CMIINISENSEIMODEtAPtJITTERCMRRCONDITIONS2.8V < VDD < 3.5V (Note 7)Differential Input (Note 7)Single Ended Input (Note 7)0V < AIN+, AIN– < VDD0V < SENSE < 1VllllllMINTYP±0.5V to ±1VMAXUNITSV10.5–10–10–101.51.51.92101010VVμAμAμAnspsRMSdB00.280DYNAMIC ACCURACY The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)PARAMETERSignal-to-Noise RatioSYMBOLSNRCONDITIONS5MHz Input12.5MHz Input70MHz Input5MHz Input12.5MHz Input70MHz Input5MHz Input12.5MHz Input70MHz Input5MHz Input12.5MHz Input70MHz InputfIN1 = 4.3MHz, fIN2 = 4.6MHzlMIN69.6TYP71.471.270.990908590909071.471.270.890MAXUNITSdBdBdBdBdBdBdBdBdBdBdBdBdBSFDRSpurious Free Dynamic Range2nd or 3rd HarmonicSpurious Free Dynamic Range4th Harmonic or HigherSignal-to-Noise Plus Distortion Ratiol74SFDRl78S/(N+D)l69.1IMDIntermodulation DistortionINTERNAL REFERENCE CHARACTERISTICS TA = 25°C. (Note 4)PARAMETERVCM Output VoltageVCM Output TempcoVCM Line RegulationVCM Output Regulation2.8V < VDD < 3.5V–1mA < IOUT < 1mACONDITIONSIOUT = 0MIN1.475TYP1.500±2534MAX1.525UNITSVppm/°CmV/VΩDIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)PARAMETERHigh Level Input VoltageLow Level Input VoltageInput CurrentInput CapacitanceCONDITIONSVDD = 3VVDD = 3VVIN = 0V to VDD(Note 7)lllSYMBOLVIHVILIINCINMIN2TYPMAXUNITSVLOGIC INPUTS (CLK, OE, SHDN)0.8–10310VμApF2226hfb3
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LTC2226Hoperating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)PARAMETERCONDITIONSDIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifi cations which apply over the full SYMBOLOVDD = 3VCOZISOURCEISINKVOHVOLOVDD = 2.5VVOHVOLOVDD = 1.8VVOHVOLHigh Level Output VoltageLow Level Output VoltageIO = –200μAIO = 1.6mA1.790.09VVHigh Level Output VoltageLow Level Output VoltageIO = –200μAIO = 1.6mA2.490.09VVHi-Z Output CapacitanceOutput Source CurrentOutput Sink CurrentHigh Level Output VoltageLow Level Output VoltageOE = High (Note 7)VOUT = 0VVOUT = 3VIO = –10μAIO = –200μAIO = 10μAIO = 1.6mAllMINTYPMAXUNITSLOGIC OUTPUTS350502.72.9952.990.0050.090.4pFmAmAVV VVPOWER REQUIREMENTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 8)PARAMETERAnalog Supply VoltageOutput Supply VoltageSupply CurrentPower DissipationShutdown PowerNap Mode PowerSHDN = H, OE = H, No CLKSHDN = H, OE = L, No CLKSYMBOLVDDOVDDIVDDPDISSPSHDNPNAPCONDITIONS(Note 9)(Note 9)llllMIN2.80.5TYP332575215MAX3.53.63090UNITSVVmAmWmWmWTIMING CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)PARAMETERSampling FrequencyCLK Low TimeSYMBOLfStLCONDITIONS(Note 9)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On(Note 7)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On(Note 7)CL = 5pF (Note 7)CL = 5pF (Note 7)(Note 7)lllllMIN118.9518.95TYP202020200MAX25500500500500UNITSMHznsnsnsnsnstHCLK High TimetAPtDSample-and-Hold Aperture DelayCLK to DATA DelayData Access Time After OE↓BUS Relinquish TimePipeline Latencylll1.42.74.33.3561210nsnsnsCycles2226hfb4
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LTC2226HELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup.Note 4: VDD = 3V, fSAMPLE = 25MHz, input range = 2VP-P with differential drive, unless otherwise noted.Note 5: Integral nonlinearity is defi ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code fl ickers between 0000 0000 0000 and 1111 1111 1111.Note 7: Guaranteed by design, not subject to test.Note 8: VDD = 3V, fSAMPLE = 25MHz, input range = 1VP-P with differential drive.Note 9: Recommended operating conditions.TYPICAL PERFORMANCE CHARACTERISTICS
Typical INL, 2V Range, 25Msps1.000.750.50
DNL ERROR (LSB)INL ERROR (LSB)0.250–0.25–0.50–0.75–1.00
0
1024
2048CODE
3072
4096
2226H G01
Typical DNL, 2V Range, 25Msps1.000.750.500.250–0.25–0.50–0.75–1.00
0
1024
2048CODE
3072
4096
2226H G02
8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 25Msps0–10–20–30AMPLITUDE (dB)–40–50–60–70–80–90–100–110–120
0
2
468FREQUENCY (MHz)
10
12
2226H G03
8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 25Msps0–10–20–30AMPLITUDE (dB)AMPLITUDE (dB)–40–50–60–70–80–90–100–110–120
0
2
468FREQUENCY (MHz)
10
12
2226H G04
8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 25Msps0–10–20–30–50–60–70–80–90–100–110–120
0
2
468FREQUENCY (MHz)
10
12
2226H G05
8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 25Msps0–10–20–30AMPLITUDE (dB)–40–50–60–70–80–90–100–110–120
0
2
468FREQUENCY (MHz)
10
12
2226H G06
–40
2226hfb5
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LTC2226HTYPICAL PERFORMANCE CHARACTERISTICS
8192 Point 2-Tone FFT,fIN = 10.9MHz and 13.8MHz, –1dB, 2V Range, 25Msps0–10–20–30AMPLITUDE (dB)–40–60–70–80–90–100–110–120
0
2
468FREQUENCY (MHz)
10
12
2226H G07
Grounded Input Histogram, 25Msps70000
617586000050000COUNT40000300002000010000
21550
2048
2049CODE
16072050
2226H G08
SNR vs Input Frequency, –1dB, 2V Range, 25Msps72
71SNR (dBFS)–50
70
69
68
0
10015050
INPUT FREQUENCY (MHz)
200
2226H G09
SFDR vs Input Frequency, –1dB, 2V Range, 25Msps1009590SFDR (dBFS)8580757065
SNR AND SFDR (dBFS)110
SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB80
SFDRSNR (dBc AND dBFS)70605040302010
SNR vs Input Level, fIN = 5MHz, 2V Range, –1dBdBFS100
90
dBc80
SNR70
050
150
INPUT FREQUENCY (MHz)
100200
2226H G10
60
010
304020
SAMPLE RATE (Msps)
50
2226H G11
0–60
–50
–40–30–20INPUT LEVEL (dBFS)
–100
2227H G12
SFDR vs Input Level, fIN = 5MHz, 2V Range, 25Msps120110100SFDR (dBc AND dBFS)90
dBcIVDD (mA)80706050403020–60
–50
–40–30–20INPUT LEVEL (dBFS)
–10
0
15
90dBc SFDRREFERENCE LINEdBFS3035
IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB3
IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V2V RANGE25
1V RANGE20
IOVDD (mA)2
1
05
10152025SAMPLE RATE (Msps)
3035
0
05
10152520
SAMPLE RATE (Msps)
3035
2226H G132226 G142226H G15
2226hfb6
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LTC2226HPIN FUNCTIONS
GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37, 48): ADC Power Ground.AIN+ (Pin 2): Positive Differential Analog Input.AIN- (Pin 3): Negative Differential Analog Input.REFH (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 7, 8 with an additional 2.2μF ceramic chip capacitor and to GND with a 1μF ce-ramic chip capacitor.REFL (Pin 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pin 5, 6 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor.VDD (Pins 10, 11, 12, 46, 47): 3V Supply. Bypass to GND with 0.1μF ceramic chip capacitors.CLK (Pin 14): Clock Input. The input sample starts on the positive edge.SHDN (Pin 16): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance.If the clock duty cycle stabilizer is used, a >1μs high pulse should be applied to the SHDN pin once the power supplies are stable at power up.OE (Pin 17): Output Enable Pin. Refer to SHDN pin func-tion.NC (Pins 19, 20): Do not connect these pins.D0–D11 (Pins 21-23, 26-28, 33-35, 38-40): Digital Out-puts. D11 is the MSB.OGND (Pin 30): Output Driver Ground.OVDD (Pin 31): Positive Supply for the Output Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.OF (Pin 41): Over/Under Flow Output. High when an over or under fl ow has occurred.MODE (Pin 42): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.SENSE (Pin 43): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range.VCM (Pins 44, 45): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip capacitor.2226hfb7
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LTC2226HFUNCTIONAL BLOCK DIAGRAM
AIN+AIN–INPUTS/HFIRST PIPELINEDADC STAGESECOND PIPELINEDADC STAGETHIRD PIPELINEDADC STAGEFOURTH PIPELINEDADC STAGEFIFTH PIPELINEDADC STAGESIXTH PIPELINEDADC STAGEVCM2.2μF1.5VREFERENCESHIFT REGISTERAND CORRECTIONRANGESELECTREFHSENSEREFBUFREFLINTERNAL CLOCK SIGNALSOVDDOFD11DIFFREFAMPCLOCK/DUTYCYCLECONTROLCONTROLLOGICOUTPUTDRIVERS•••D0REFH0.1μFREFLCLKMODESHDNOEOGND2226H F012.2μF1μF1μFFigure 1. Functional Block DiagramTIMING DIAGRAM
tAPANALOGINPUT
NtHtLCLK
tDD0-D11, OF
N – 5N – 4N – 3N – 2N – 1N2226H TD01N + 2N + 3N + 1N + 4N + 52226hfb8
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LTC2226HAPPLICATIONS INFORMATION
DYNAMIC PERFORMANCESignal-to-Noise Plus Distortion RatioThe signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen-tal input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.Signal-to-Noise RatioThe signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the fi rst fi ve harmonics and DC.Total Harmonic DistortionTotal harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:⎛
THD = 20Log⎜
⎝ is defi ned as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.Spurious Free Dynamic Range (SFDR)Spurious free dynamic range is the peak harmonic or spuri-ous noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.Input BandwidthThe input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.Aperture Delay TimeThe time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit.Aperture Delay JitterThe variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:SNRJITTER = –20log (2π • fIN • tJITTER)CONVERTER OPERATIONAs shown in Figure 1, the LTC2226H is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value fi ve cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2226H has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifi er. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the 2226hfb(V2
2
⎞
+V32+V42+...Vn2/V1⎟⎠
)where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fi fth.Intermodulation DistortionIf the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion 9
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LTC2226HAPPLICATIONS INFORMATION
DAC to produce a residue. The residue is amplifi ed and output by the residue amplifi er. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifi er which drives the fi rst pipelined ADC stage. The fi rst stage acquires the output of the S/H dur-ing this high phase of CLK. When CLK goes back low, the fi rst stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fi fth stages, resulting in a fi fth stage residue that is sent to the sixth stage ADC for fi nal evaluation.Each ADC stage following the fi rst has additional range to accommodate fl ash and amplifi er offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.SAMPLE/HOLD OPERATION AND INPUT DRIVESample/Hold OperationFigure 2 shows an equivalent circuit for the LTC2226H CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, LTC2226HVDD15ΩCPARASITIC1pFCSAMPLE4pFCPARASITIC1pFCSAMPLE4pFAIN+VDD15ΩAIN–CLK2226H F02
Figure 2. Equivalent Input Circuitthe inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.Single-Ended InputFor cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the har-monic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to VCM or a low noise reference voltage between 1V and 1.5V.Common Mode BiasFor optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pins 44, 45) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pins must be bypassed to ground close to the ADC with a 2.2μF or greater capacitor.2226hfb10
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LTC2226HAPPLICATIONS INFORMATION
Input Drive ImpedanceAs with all high performance, high speed ADCs, the dy-namic performance of the LTC2226H can be infl uenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can infl uence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.Input Drive CircuitsFigure 3 shows the LTC2226H being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the trans-former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and VCM2.2μF0.1μF
ANALOGINPUT
T11:125Ω25Ω25Ω0.1μF12pF25ΩAIN–25Ω2226H F03
hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.Figure 4 demonstrates the use of a differential amplifi er to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. VCMHIGH SPEEDDIFFERENTIAL25ΩAMPLIFIERANALOGINPUT2.2μFAIN+LTC2226H+CM+–12pF25ΩAIN–2226H F04
–Figure 4. Differential Drive with an Amplifi erVCM1k1k25Ω2.2μFAIN+AIN+LTC2226H0.1μFANALOGINPUT
LTC2226H12pFAIN–2226H F05T1 = MA/COM ETC1-1TRESISTORS, CAPACITORSARE 0402 PACKAGE SIZE
0.1μFFigure 3. Single-Ended to Differential Conversion Using a TransformerFigure 5. Single-Ended Drive2226hfb11
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LTC2226HAPPLICATIONS INFORMATION
Reference OperationFigure 6 shows the LTC2226H reference circuitry consist-ing of a 1.5V bandgap reference, a difference amplifi er and switching and control circuit. The internal voltage reference can be confi gured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range.The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifi er to gener-ate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.The difference amplifi er generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed.Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 7. An external reference can be used by apply-ing its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1μF ceramic capacitor.Input RangeThe input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB.1.5VLTC2226H1.5VVCM2.2μF4Ω1.5V BANDGAPREFERENCE1VRANGEDETECTANDCONTROLSENSEBUFFERINTERNAL ADCHIGH REFERENCEREFH4.7μFFERRITEBEAD0.1μF2.2μF0.1μFDIFF AMPCLK1μFREFLINTERNAL ADCLOW REFERENCE2226H F06
VCM2.2μFSENSE1μFLTC2226H12k0.75V0.5V12k2226H F07Figure 7. 1.5V Range ADCCLEANSUPPLYTIE TO VDD FOR 2V RANGE;TIE TO VCM FOR 1V RANGE;RANGE = 2 • VSENSE FOR0.5V < VSENSE < 1V1μF100ΩLTC2226H2226H F08IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 6. Equivalent Reference CircuitFigure 8. CLK Drive Using an LVDS or PECL to CMOS Converter2226hfb12
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LTC2226HAPPLICATIONS INFORMATION
Driving the Clock InputThe CLK input can be driven directly with a CMOS or TTL level signal. A differential clock can also be used along with a low-jitter CMOS converter before the CLK pin (see Figure 8).The noise performance of the LTC2226H can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. Maximum and Minimum Conversion RatesThe maximum conversion rate for the LTC2226H is 25Msps. For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 18.9ns for the ADC internal circuitry to have enough settling time for proper operation.An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors.If the clock duty cycle stabilizer is used, a >1μs high pulse should be applied to the SHDN pin once the power supplies are stable at power up.The lower limit of the LTC2226H sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specifi ed minimum operating frequency for the LTC2226H is 1Msps.DIGITAL OUTPUTSTable 1 shows the relationship between the analog input voltage, the digital data bits, and the overfl ow bit.2226H F09
Table 1. Output Codes vs Input VoltageAIN+ – AIN–(2V Range)>+1.000000V+0.999512V+0.999024V+0.000488V0.000000V–0.000488V–0.000976V–0.999512V–1.000000V<–1.000000VOF1000000001D11 – D0(Offset Binary)11 11 1111 111111 11 1111 111111 11 1111 111010 00 0000 000110 00 0000 000001 11 1111 111101 11 1111 11100000 0000 00010000 0000 00000000 0000 0000D11 – D0(2’s Complement)0111 1111 11110111 1111 11110111 1111 111000 00 0000 000100 00 0000 000011 11 1111 111111 11 1111 11101000 0000 00011000 0000 00001000 0000 0000Digital Output BuffersFigure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2226H should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs.LTC2226HVDDVDDOVDD0.5VTO 3.6V0.1μFOVDDDATAFROMLATCHOEPREDRIVERLOGIC43ΩTYPICALDATAOUTPUTOGNDFigure 9. Digital Output Buffer2226hfb13
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LTC2226HAPPLICATIONS INFORMATION
Data FormatUsing the MODE pin, the LTC2226H parallel digital output can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.Table 2. MODE Pin FunctionMODE PIN01/3VDD2/3VDDVDDOUTPUT FORMATOffset BinaryOffset Binary2’s Complement2’s ComplementCLOCK DUTYCYCLE STABILIZEROffOnOnOffSleep and Nap ModesThe converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dis-sipates 15mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.Grounding and BypassingThe LTC2226H requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-tors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2μF capacitor be-tween REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.The LTC2226H differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.Overfl ow BitWhen OF outputs a logic high the converter is either over-ranged or underranged.Output Driver PowerSeparate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply.OVDD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.Output EnableThe outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF.2226hfb14
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LTC2226HPACKAGE DESCRIPTION
LX Package48-Lead Plastic LQFP (7mm × 7mm)(Reference LTC DWG # 05-08-1760 Rev Ø)7.15– 7.255.50 REF489.00 BSC7.00 BSC0.50 BSC124812SEE NOTE: 49.00 BSC5.50 REF0.20 – 0.307.15– 7.25AA7.00 BSCPACKAGE OUTLINEC0.30 – 0.501.30 MINRECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
11° – 13°1.60
1.35 – 1.45MAXR0.08 – 0.20GAUGE PLANE0.250° – 7°11° – 13°1.00 REF0.45 – 0.75SECTION A – A
0.09 – 0.200.50BSC0.17 – 0.270.05 – 0.15LX48 LQFP 0907 REVØ
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE2. DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER5. DRAWING IS NOT TO SCALE
2226hfbInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.15
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LTC2226HRELATED PARTS
PART NUMBERLTC1748LTC1750LT1993-2LT1994LTC2202LTC2208LTC2220-1LTC2224LTC2225LTC2226LTC2227LTC2228LTC2229LTC2236LTC2237LTC2238LTC2239LTC2245LTC2246LTC2247LTC2248LTC2249LTC2250LTC2251LTC2252LTC2253LTC2254LTC2255LTC2284LT5512LT5514LT5515LT5516LT5517LT5522DESCRIPTION14-Bit, 80Msps, 5V ADC14-Bit, 80Msps, 5V Wideband ADCHigh Speed Differential Op AmpLow Noise, Low Distortion Fully Differential Input/Output Amplifi er/Driver16-Bit, 10Msps, 3.3V ADC, Lowest Noise16-Bit, 130Msps, 3.3V ADC, LVDS Outputs12-Bit, 185Msps, 3.3V ADC, LVDS Outputs12-Bit, 135Msps, 3.3V ADC, High IF Sampling12-Bit, 10Msps, 3V ADC, Lowest Power12-Bit, 25Msps, 3V ADC, Lowest Power12-Bit, 40Msps, 3V ADC, Lowest Power12-Bit, 65Msps, 3V ADC, Lowest Power12-Bit, 80Msps, 3V ADC, Lowest Power10-Bit, 25Msps, 3V ADC, Lowest Power10-Bit, 40Msps, 3V ADC, Lowest Power10-Bit, 65Msps, 3V ADC, Lowest Power10-Bit, 80Msps, 3V ADC, Lowest Power14-Bit, 10Msps, 3V ADC, Lowest Power14-Bit, 25Msps, 3V ADC, Lowest Power14-Bit, 40Msps, 3V ADC, Lowest Power14-Bit, 65Msps, 3V ADC, Lowest Power14-Bit, 80Msps, 3V ADC, Lowest Power10-Bit, 105Msps, 3V ADC, Lowest Power10-Bit, 125Msps, 3V ADC, Lowest Power12-Bit, 105Msps, 3V ADC, Lowest Power12-Bit, 125Msps, 3V ADC, Lowest Power14-Bit, 105Msps, 3V ADC, Lowest Power14-Bit, 125Msps, 3V ADC, Lowest Power14-Bit, Dual, 105Msps, 3V ADC, Low CrosstalkDC-3GHz High Signal Level Downconverting MixerUltralow Distortion IF Amplifi er/ADC Driverwith Digitally Controlled Gain1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator800MHz to 1.5GHz Direct Conversion Quadrature Demodulator40MHz to 900MHz Direct Conversion Quadrature Demodulator600MHz to 2.7GHz High Linearity Downconverting MixerCOMMENTS76.3dB SNR, 90dB SFDR, 48-Pin TSSOP PackageUp to 500MHz IF Undersampling, 90dB SFDR800MHz BW, –70dBc Distortion at 70MHz, 6dB GainLow Distortion: –94dBc at 1MHz150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN60mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN75mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN205mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFNDC to 3GHz, 21dBm IIP3, Integrated LO Buffer450MHz to 1dB BW, 47dB OIP3, Digital Gain Control10.5dB to 33dB in 1.5dB/StepHigh IIP3: 20dBm at 1.9GHz,High IIP3: 21.5dBm at 900MHz,High IIP3: 21dBm at 800MHz,4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,NF = 12.5dB, 50Ω Single-Ended RF and LO Ports2226hfb16
Linear Technology CorporationLT 0708 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com© LINEAR TECHNOLOGY CORPORATION 2007
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