Evaluation Board for CS5340
Features
Demonstrates recommended layout and
Description
The CDB5340 evaluation board is an excellent meansfor quickly evaluating the CS5340 24-bit, stereo A/D con-verter. Evaluation requires a digital signal analyzer, ananalog signal source, and a power supply.
Also included is a CS8406 digital audio interface trans-mitter which generates S/PDIF, and EIAJ-340compatible audio data. The digital audio data is availablevia RCA phono and optical connectors.
grounding arrangements
CS8406 generates S/PDIF, and EIAJ-340 compatible digital audio
Requires only an analog signal source and power supplies for a complete Analog-to-Digital-Converter system
ORDERING INFORMATION
CDB5340 Evaluation Board
ANALOG INPUT
CS5340
CS8406AES/EBU S/PDIF
TRANSMITTER
S/PDIFOUTPUT
I/O FORCLOCKSAND DATA
Cirrus Logic, Inc.www.cirrus.com
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
JUL ‘03DS601DB1
1
CDB5340
TABLE OF CONTENTS
1. CDB5340 SYSTEM OVERVIEW ..............................................................................................32. CS8406 DIGITAL AUDIO TRANSMITTER ...............................................................................33. INPUT/OUTPUT FOR CLOCKS AND DATA ...........................................................................34. POWER SUPPLY CIRCUITRY .................................................................................................35. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................36. ANALOG INPUT FILTER .........................................................................................................3
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow..........................................................................5Figure 2. Analog Audio Input...........................................................................................................6Figure 3. CS5340............................................................................................................................7Figure 4. Level Shifters...................................................................................................................8Figure 5. CS8406 Digital Audio Interface........................................................................................9Figure 6. Power Circuit..................................................................................................................10Figure 7. Top Layer Silkscreen.....................................................................................................11Figure 8. Top Layer......................................................................................................................12Figure 9. Bottom Layer.................................................................................................................13
LIST OF TABLES
Table 1. System Connections ........................................................................................................4Table 2. CDB5340 Jumper and Switch Settings ............................................................................4
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.comIMPORTANT NOTICECirrus Logic, Inc. and its subsidiaries (\"Cirrus\") believe that the information contained in this document is accurate and reliable. However, the information is subjectto change without notice and is provided \"AS IS\" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevantinformation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of salesupplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed byCirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rightsof third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask workrights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and givesconsent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consentdoes not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this materialand controlled under the \"Foreign Exchange and Foreign Trade Law\" is to be exported or taken out of Japan. An export license and/or quota needs to be obtainedfrom the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Lawand is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-ERTY OR ENVIRONMENTAL DAMAGE (\"CRITICAL APPLICATIONS\"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USEIN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRIT-ICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITYDEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DIS-CLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT-NESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'SCUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEM-NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS'FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarksor service marks of their respective owners.2DS601DB1
CDB5340
1.CDB5340 SYSTEM OVERVIEW
The CDB5340 evaluation board is an excellent means of quickly evaluating the CS5340. TheCS8406 digital audio interface transmitter provides an easy interface to digital audio signal ana-lyzers including the majority of digital audio test equipment.
The CDB5340 schematic has been partitioned into 5 schematics shown in Figure2 throughFigure6. Each partitioned schematic is represented in the system diagram shown in Figure1.Notice that the system diagram also includes the interconnections between thepartitionedschematics.
2.CS8406 DIGITAL AUDIO TRANSMITTER
The system generates and encodes standard S/PDIF data using a CS8406 Digital Audio Trans-mitter (seeFigure5). The outputs of the CS8406 are RS422 compatible differential line drivers.The CS8406 supports both Left Justified and I2S data formats, as determined by the DIP switch,S2. A description of the CS8406 is included in the CS8406 datasheet.
3.INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pinheader, J11. The schematic for the clock/data input/output is shown in Figure4.
The CDB5340 allows some flexibility as to the generation of the clocks. When the CS5340 andCS8406 are in slave mode, the SCLK and LRCK must be provided via the header, J11. MCLKcan be generated from the on-board oscillator, Y1 or provided via the header, J11 as determinedby the DIP switch, S2. The on-board oscillator is socketed to allow other frequency oscillators tobe used. Please note that the on-board oscillator must be removed if an external MCLK is pro-vided through header J11.
4.POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts (VA/VD, VL, GND, +5V),seeFigure6. The VA/VD input supplies the VA and VD pins of the CS5340. VL supplies powerto the VL pin of the CS5340 and to the level shifter circuits. The +5V input supplies power to thedigital circuitry and the input amplifiers.
5.GROUNDING AND POWER SUPPLY DECOUPLING
The CS5340 requires careful attention to power supply and grounding arrangements to optimizeperformance. Figure3 details the power distribution used on this board. The decoupling capac-itors are located as close to the CS5340 as possible. Extensive use of ground plane fill in theevaluation board yields large reductions in radiated noise.
6.ANALOG INPUT FILTER
The CDB5340 implements a single-ended analog input buffer, as shown in Figure2. Note thatthere is no attenuation or gain associated with the input buffer.
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CDB5340
CONNECTORVA/VDVLGND+5VAINLAINR
Optical OutputCoax Output
INPUT/OUTPUTInputInputInputInputInputInputOutputOutput
SIGNAL PRESENT
+3.3V to +5V power for the CS5340+2.5V to +5V power for the CS5340Ground connection from power supply+ 5 Volt power
Analog input left channelAnalog input right channelDigital audio outputDigital audio output
Table 1. System Connections
JUMPER/SWITCHJ5
PURPOSE
VA/VD Power Source
POSITIONADJ*+3.3V+5VADJ*+3.3V+5V--M1/M0
FUNCTION SELECTED
Power from the Binding Post (J1)Power from the +3.3V RegulatorPower from the +5V SupplyPower from the Binding Post (J2)Power from the +3.3V RegulatorPower from the +5V Supply--OpenHi*ClosedLow
J6VL Power Source
J11S1S2
Input/Output for clocks/data
Reset for the CDB5340CDB5340 Configuration
SCLK/LRCKOpenHeader J11 is an input for clocks.
*ClosedHeader J11 is an output for clocks.MCLK8406DIF
OpenHeader J11 is an input for MCLK.*ClosedHeader J11 is an output for MCLK.OpenCS8406 in Master mode*ClosedCS8406 in Slave mode
OpenDigital interface format set to I2S*ClosedDigital interface format set to
LeftJustified
Table 2. CDB5340 Jumper and Switch Settings
* denotes default factory settings
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RESETCIRCUITFIG 6CS8406CS5340SHIFTERFIG 4FIG 3LEVELANALOG INPUTDIGITALAUDIOINTERFACEFIG 2FIG 5I/O FORCLOCKSAND DATAFIG 4CRYSTALOSCILLATORFIG 4Figure 1. System Block Diagram and Signal FlowCDB5340
5
6
Figure 2. Analog Audio InputCDB5340DS601DB1
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CS5340-CZCS5340 Data ModesFigure 3. CS5340CDB53407
8
CDB5340
Figure 4. Level ShiftersDS601DB1
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CDB5340Figure 5. CS8406 Digital Audio Interface9
10
Figure 6. Power CircuitCDB5340
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DS601DB1CDB5340CS5340CS5340 Data ModesCDB5340CDB5340CDB5340
Figure 7. Top Layer Silkscreen1112CDB5340
Figure 8. Top LayerDS601DB1DS601DB1
CDB5340
Figure 9. Bottom Layer13
CDB4398
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