Features
•Industry Standard Architecture
–Emulates Many 20-Pin PALs®
–Low Cost Easy-to-Use Software Tools
•High-Speed Electrically Erasable Programmable Logic Devices
–7.5 ns Maximum Pin-to-Pin Delay •Several Power Saving OptionsDeviceICC, Stand-By
ICC, ActiveATF16V8B50 mA55 mAATF16V8BQ35 mA40 mAATF16V8BQL
5 mA
20 mA
•CMOS and TTL Compatible Inputs and Outputs–Input and I/O Pull-Up Resistors•Advanced Flash Technology–Reprogrammable–100% Tested
•
High Reliability CMOS Process–20 Year Data Retention–100 Erase/Write Cycles–2,000V ESD Protection–200 mA Latchup Immunity
•Commercial, and Industrial Temperature Ranges
•
Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
Pin ConfigurationsTSSOP Top View
Pin NameFunctionI/CLK120VCCI1219I/OI2318I/OCLKClockI3417I/OI4516I/OI5615I/OILogic InputsI6714I/OI7813I/OI/OBidirectional BuffersI8912I/OGND1011I9/OEOEOutput EnableVDIP/SOICPLCC Top ViewCC+5 V SupplyHigh-Performance Flash PLDATF16V8BRev. 0364E–07/981
元器件交易网www.cecb2b.com
Description
The ATF16V8B is a high performance CMOS (ElectricallyErasable) Programmable Logic Device (PLD) which utilizesAtmel’s proven electrically erasable Flash memory technol-ogy. Speeds down to 7.5 ns are offered. All speed rangesare specified over the full 5V ± 10% range for industrialtemperature ranges, and 5V ± 5% for commercial tempera-ture ranges.
Several low power options allow selection of the best solu-tion for various types of power-limited applications. Each of
these options significantly reduces total system power andenhances system reliability.
The ATF16V8Bs incorporate a superset of the genericarchitectures, which allows direct replacement of the 16R8family and most 20-pin combinatorial PLDs. Eight outputsare each allocated eight product terms. Three differentmodes of operation, configured automatically with soft-ware, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias.................................-55oC to +125oCStorage Temperature......................................-65oC to +150oCVoltage on Any Pin with
Respect to Ground.......................................-2.0 V to +7.0 V(1)Voltage on Input Pins with Respect to Ground
During Programming...................................-2.0 V to +14.0 V(1)
Note:
Programming Voltage with
Respect to Ground.....................................-2.0 V to +14.0 V(1)
1.
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Minimum voltage is -0.6V DC, which may under-shoot to -2.0V for pulses of less than 20 ns. Max-imum output pin voltage is VCC+ 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial
Operating Temperature (Case)VCC Power Supply
0oC - 70oC5V ± 5%
Industrial-40oC - 85oC5V ± 10%
2
ATF16V8B
元器件交易网www.cecb2b.com
ATF16V8B
DC Characteristics
SymbolIILIIH
ParameterInput or I/O Low Leakage CurrentInput or I/O HighLeakage Current
Condition0 ≤ VIN ≤ VIL(MAX)3.5 ≤ VIN ≤ VCC
B-7, -10
VCC = MAX, VIN = MAX, Outputs Open
Com.Ind.Com.Ind.Com.Com.Ind.Com.Ind.Com.Ind.Com.Com.Ind.
55555050355560605555402020
Min
Typ-35
Max-1001085957580551015901008595553540-130
-0.52.0
VIN=VIH or VIL,VCC=MINVIN=VIH or VIL,VCC=MIN
IOL = -24 mACom., Ind.IOH = -4.0 mA
2.4
0.8VCC+0.750.5
UnitsµAµAmAmAmAmAmAmAmAmAmAmAmAmAmAmAmAVVVV
ICC
Power Supply Current, Standby
B-15, -25BQ-10BQL-15, -25
B-7, -10
VCC = MAX, Outputs Open, f=15 MHz
ICC2
Clocked Power Supply Current
B-15, -25BQ-10BQL-15, -25
IOS(1)VILVIHVOLVOHNote:
Output Short Circuit CurrentInput Low VoltageInput High VoltageOutput High VoltageOutput High Voltage
VOUT = 0.5 V
1.Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
3
元器件交易网www.cecb2b.com
AC Waveforms(1)
Note:1.Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.
AC Characteristics(1)
-7(2)
SymboltPDtCFtCOtStHtPtW
Parameter
Input or Feedback to Non-Registered OutputClock to FeedbackClocktoOutputInput or Feedback Setup TimeHoldTimeClockPeriodClock Width
External Feedback 1/(tS+tCO)
FMAX
Internal Feedback 1/(tS + tCF)No Feedback 1/(tP)
tEAtERtPZXtPXZNotes:
Input to Output Enable —Product Term
Input to Output Disable —Product Term
OE pin to Output EnableOE pin to Output Disable2.Recommend ATF16V8C-7.
3221.525084
1001251259966
3221.5
8 outputs switching1 output switching
Min3
Max7.5735
27.50126
68748310101010
3221.567
2120168
45506215151515
3221.5810
21502412
374041202020201012
Min3-10Max10
Min3-15Max15
Min3-25Max25
Units nsnsnsnsnsnsnsnsMHzMHzMHznsnsnsns
1.See ordering information for valid part numbers and speed grades.
4
ATF16V8B
元器件交易网www.cecb2b.com
ATF16V8B
Output Test Loads:
Commercial
Input Test Waveforms and Measurement Levels:
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
CINCOUTNote:
56
Max88
UnitspFpF
ConditionsVIN = 0 VVOUT = 0 V
1.Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF16V8Bs are designed to reset dur-ing power up. At a point delayed slightly from VCC crossingVRST, all registers will be reset to the low state. As a result,the registered output state will always be high on power-up.This feature is critical for state machine initialization. How-ever, due to the asynchronous nature of reset and theuncertainty of how VCC actually rises in the system, the fol-lowing conditions are required:
1)The VCC rise must be monotonic,
2)After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and3)The clock must remain stable during tPR.
ParametertPRVRST
DescriptionPower-UpReset TimePower-UpReset Voltage
Typ6003.8
Max1,0004.5
UnitsnsV
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry toallow loading of each register with either a high or a low.This feature will simplify testing since any state can beforced into the registers to control test sequencing. AJEDEC file with preload is generated when a source filewith vectors is compiled. Once downloaded, the JEDEC filepreload sequence will be done automatically by most of theapproved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copyingof the ATF16V8B fuse patterns. Once programmed, fuseverify and preload are inhibited. However, the 64-bit UserSignature remains accessible.
The security fuse should be programmed last, as its effectis immediate.
5
元器件交易网www.cecb2b.com
Electronic Signature Word
There are 64 bits of programmable memory that are alwaysavailable to the user, even if the device is secured. Thesebits can be used for user-specific data.
Input and I/O Pull-Ups
All ATF16V8B family members have internal input and I/Opull-up resistors. Therefore, whenever inputs or I/Os arenot being driven externally, they will float to VCC. Thisensures that all logic array inputs are at known states.These are relatively weak active pull-ups that can easily beoverdriven by TTL-compatible drivers (see input and I/Odiagrams below).
Programming/Erasing
Programming/erasing is performed using standard PLDprogrammers. See CMOS PLD Programming Hardwareand Software Support for information on software/program-ming.
Input DiagramI/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe theATF16V8B architecture. Eight configurable macrocells canbe configured as a registered output, combinatorial I/O,combinatorial output, or dedicated input.
The ATF16V8B can be configured in one of three differentmodes. Each mode makes the ATF16V8B look like a differ-ent device. Most PLD compilers can choose the rightmode automatically. The user can also force the selectionby supplying the compiler with a mode selection. The deter-mining factors would be the usage of register versus com-binatorial outputs and dedicated outputs versus outputswith output enable control.
The ATF16V8B universal architecture can be programmedto emulate many 20-pin PAL devices. These architectural
subsets can be found in each of the configuration modesdescribed in the following pages. The user can downloadthe listed subset device JEDEC programming file to thePLD programmer, and the ATF16V8B can be configured toact like the chosen device. Check with your programmermanufacturer for this capability.
Unused product terms are automatically disabled by thecompiler to decrease power consumption. A Security Fuse,when programmed, protects the content of the ATF16V8B.Eight bytes (64 fuses) of User Signature are accessible tothe user for purposes such as storing project name, partnumber, revision, or date. The User Signature is accessibleregardless of the state of the Security Fuse.
Compiler Mode Selection
Registered
ABEL, Atmel-ABELCUPLLOG/iCOrCAD-PLDPLDesignerTango-PLDNote:
P16V8RG16V8MSGAL16V8_R(1)“Registered”P16V8RG16V8R
ComplexP16V8CG16V8MAGAL16V8_C7(1)“Complex”P16V8CG16V8C
SimpleP16V8ASG16V8ASGAL16V8_C8(1)“Simple”P16V8CG16V8AS
Auto SelectP16V8G16V8GAL16V8GAL16V8AP16V8AG16V8
1.Only applicable for version 3.4 or lower.
6
ATF16V8B
元器件交易网www.cecb2b.com
ATF16V8B
In simple mode all feedback paths of the output pins arerouted via the adjacent pins. In doing so, the two inner mostpins (pins 15 and 16) will not have the feedback option asthese pins are always configured as dedicated combinato-rial output.
Macrocell Configuration
Software compilers support the three different OMCmodes as different device types. Most compilers have theability to automatically select the device type, generallybased on the register usage and output enable (OE) usage.Register usage on the device forces the software to choosethe registered mode. All combinatorial outputs with OEcontrolled by the product term will force the software tochoose the complex mode. The software will choose thesimple mode only when all outputs are dedicated combina-torial without OE control. The different device types can beused to override the automatic device selection by the soft-ware. For further details, refer to the compiler softwaremanuals.
When using compiler software to configure the device, theuser must pay special attention to the following restrictionsin each mode.
In registered mode pin 1 and pin 11 are permanently con-figured as clock and output enable, respectively. Thesepins cannot be configured as dedicated inputs in the regis-tered mode.
In complex mode pin 1 and pin 11 become dedicatedinputs and use the feedback paths of pin 19 and pin 12respectively. Because of this feedback path usage, pin 19and pin 12 do not have the feedback option in this mode.
ATF16V8B Registered Mode
PAL Device Emulation / PAL Replacement
The registered mode is used if one or more registers arerequired. Each macrocell can be configured as either a reg-istered or combinatorial output or I/O, or as an input. For aregistered output or I/O, the output is enabled by the OEpin, and the register is clocked by the CLK pin. Eight prod-uct terms are allocated to the sum term. For a combinato-rial output or I/O, the output enable is controlled by aproduct term, and seven product terms are allocated to thesum term. When the macrocell is configured as an input,the output enable is permanently disabled.
Any register usage will make the compiler select this mode.The following registered devices can be emulated usingthis mode:16R8 16RP8 16R6 16RP6 16R4 16RP4
Registered Configuration for Registered Mode(1)(2)Combinatorial Configuration for Registered Mode(1)(2)
Notes:1.
Pin 1 cotrols common CLK for the registered out-puts. Pin 11 controls common OE for the registered outputs. Pin 1 and Pin 11 are permanently config-ured as CLK and OE.The development software configures all the archi-tecture control bits and checks for proper pin usage automatically.
Notes:1.2.
Pin 1 and Pin 11 are permanently configured as CLK and OE.The development software configures all the archi-tecture control bits and checks for proper pin usage automatically.
2.
7
元器件交易网www.cecb2b.com
Registered Mode Logic Diagram
8
ATF16V8B
元器件交易网www.cecb2b.com
ATF16V8B
ATF16V8B Complex Mode
PAL Device Emulation/PAL Replacement
In the Complex Mode, combinatorial output and I/O func-tions are possible. Pins 1 and 11 are regular inputs to thearray. Pins 13 through 18 have pin feedback paths back tothe AND-array, which makes full I/O capability possible.Pins 12 and 19 (outermost macrocells) are outputs only.They do not have input capability. In this mode, each mac-rocell has seven product terms going to the sum term andone product term enabling the output.
Combinatorial applications with an OE requirement willmake the compiler select this mode. The following devicescan be emulated using this mode: 16L8 16H8 16P8
Complex Mode Option
ATF16V8B Simple Mode
PAL Device Emulation / PAL Replacement
In the Simple Mode, 8 product terms are allocated to thesum term. Pins 15 and 16 (center macrocells) are perma-nently configured as combinatorial outputs. Other macro-cells can be either inputs or combinatorial outputs with pinfeedback to the AND-array. Pins 1 and 11 are regularinputs.
The compiler selects this mode when all outputs are combi-natorial without OE control. The following simple PALs canbe emulated using this mode: 10L8 10H8 10P812L6 12H6 12P6 14L4 14H4 14P4 16L2 16H2 16P2
Simple Mode Option
* - Pins 15 and 16 are always enabled.
9
元器件交易网www.cecb2b.com
Complex Mode Logic Diagram
10ATF16V8B元器件交易网www.cecb2b.com
ATF16V8B
Simple Mode Logic Diagram
11
元器件交易网www.cecb2b.com
SUPPLYCURRENTvs.INPUTFREQUENCY75SUPPLYCURRENTvs.INPUTFREQUENCY75ATF16V8B/BQ (VCC= 5V, TA = 25C)ATF16V8BATF16V8BL/BQL (VCC= 5V, TA = 25C)ATF16V8BLICCmA50ICC50ATF16V8BQ25ATF16V8BQL25mA002550751000020406080100FREQUENCY (MHz)FREQUENCY (MHz)SUPPLYCURRENTvs.SUPPLYVOLTAGE65ATF16V8B/BQ(TA=25C)ATF16V8BICCmA5545ATF16V8BQ35254.504.755.005.255.50SUPPLYVOLTAGE(V)OUTPUTSOURCECURRENT-10-12vs.SUPPLYVOLTAGE(TA=25C)IOHmA-14-16-18-20-22-244.54.74.95.15.35.5SUPPLYVOLTAGE(V)12
ATF16V8B
元器件交易网www.cecb2b.com
NORMALIZEDTPDvs.SUPPLY VOLTAGE (TA=25°C)1.3NO1.15RMATF16V8B/BQ1TATF16V8BQLP0.85D0.74.504.755.005.255.50SUPPLY VOLTAGE (V)vs.NORMALIZEDSUPPLYVOLTAGE(TA=25°C)TCO1.3NO1.15RATF16V8B/BQM1TATF16V8BQLC0.85O0.74.504.755.005.255.50SUPPLYVOLTAGE(V)ATF16V8B
13
元器件交易网www.cecb2b.com
14
ATF16V8B
元器件交易网www.cecb2b.com
ATF16V8B
Ordering Information
tPD(ns)7.5
tS(ns)5
tCO(ns)5
Ordering CodeATF16V8B-7JC(1)ATF16V8B-7PC(1)ATF16V8B-7SC(1)ATF16V8B-7XC(1)ATF16V8B-10JCATF16V8B-10PCATF16V8B-10SCATF16V8B-10XCATF16V8B-10JIATF16V8B-10PIATF16V8B-10SIATF16V8B-10XI
15
12
10
ATF16V8B-15JCATF16V8B-15PCATF16V8B-15SCATF16V8B-15XCATF16V8B-15JIATF16V8B-15PIATF16V8B-15SIATF16V8B-15XI
25
15
12
ATF16V8B-25JCATF16V8B-25PCATF16V8B-25SCATF16V8B-25XCATF16V8B-25JIATF16V8B-25PIATF16V8B-25SIATF16V8B-25XI
Note:
1.Recommend ATF16V8C-7.
Package20J20P320S20X20J20P320S20X20J20P320S20X20J20P320S20X20J20P320S20X20J20P320S20X20J20P320S20X
Operation RangeCommercial(0°C to 70°C)
107.57
Commercial(0°C to 70°C)
Industrial(-40°C to 85°C)
Commercial(0°C to 70°C)
Industrial(-40°C to 85°C)
Commercial(0°C to 70°C)
Industrial(-40°C to 85°C)
15
元器件交易网www.cecb2b.com
Ordering Information
tPD(ns)10
tS(ns)7.5
tCO(ns)7
Ordering CodeATF16V8BQ-10JCATF16V8BQ-10PCATF16V8BQ-10SCATF16V8BQ-10XCATF16V8BQL-15JCATF16V8BQL-15PCATF16V8BQL-15SCATF16V8BQL-15XCATF16V8BQL-25JCATF16V8BQL-25PCATF16V8BQL-25SCATF16V8BQL-25XCATF16V8BQL-25JIATF16V8BQL-25PIATF16V8BQL-25SIATF16V8BQL-25XI
Package20J20P320S20X20J20P320S20X20J20P320S20X20J20P320S20X
Operation RangeCommercial(0°C to 70°C)
151210
Commercial(0°C to 70°C)
251512
Commercial(0°C to 70°C)
Industrial(-40°C to 85°C)
Package Type
20J20P320S20X
20-Lead, Plastic J-Leaded Chip Carrier (PLCC)
20-Lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)20-Lead, 0.300\" Wide, Plastic Gull Wing Small Outline (SOIC)20-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
16
ATF16V8B
元器件交易网www.cecb2b.com
ATF16V8B
Packaging Information
20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-018 AA20P3, 20-Lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-001 AD1.060(26.9).980(24.9)PIN1.280(7.11).240(6.10).090(2.29)MAX.005(.127)MIN.900(22.86) REF.210(5.33)MAXSEATINGPLANE.150(3.81).115(2.92).110(2.79).090(2.29).070(1.78).045(1.13).325(8.26).300(7.62).014(.356).008(.203)0REF15.015(.381) MIN.022(.559).014(.356).430(10.92) MAX20S, 20-Lead, 0.300\" Wide, Plastic Gull Wing Small Outline (SOIC)Dimensions in Inches and (Millimeters)0.020 (0.508)0.013 (0.330)20X, 20-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)Dimensions in Millimeters and (Inches)0.30(0.012)0.18(0.007)PIN 10.299 (7.60)0.420 (10.7)0.291 (7.39)0.393 (9.98)4.48(.176)6.50(.256)4.30(.169)6.25(.246)PIN 1 ID.050 (1.27) BSC0.65(.0256) BSC0.513 (13.0)0.497 (12.6)0.105 (2.67)0.092 (2.34)6.60(.260)6.40(.252)1.10(0.043) MAX0.012 (0.305)0.003 (0.076)0.15(.006)0.05(.002)0REF80.013 (0.330)0.009 (0.229)0.18(.007)0.09(.003)0REF80.70(.028)0.50(.020)0.035 (0.889)0.015 (0.381)17
因篇幅问题不能全部显示，请点此查看更多更全内容