Dynamic random access memory having decoding circu

专利名称：Dynamic random access memory having

decoding circuitry for partial memory blocks

发明人：Adrian E Ong,Paul S. Zagar,Troy

Manning,Brent Keeth,Ken Waller

申请号：US08/869035申请日：19970605公开号：US05901105A公开日：19990504

摘要：A semiconductor dynamic random-access memory (DRAM) device embodyingnumerous features that collectively and/or individually prove beneficial and

advantageous with regard to such considerations as density, power consumption, speed,and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantiallyidentical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbitquadrant of the device. Between the top two quadrants and between the bottom twoquadrants are column blocks containing I/O read/write circuitry, column redundancyfuses, and column decode circuitry. Column select lines originate from the column blocksand extend right and left across the width of each quadrant. Each PAB comprises eightsubstantially identical 1 Mbit sub- array blocks (SABs). Associated with each SAB are aplurality of local row decoder circuits functioning to receive partially decoded rowaddresses from a column predecoder circuit and generating local row addressessupplied to the SAB with which they are associated. Various pre- and/or post-packagingoptions are provided for enabling a large degree of versatility, redundancy, and economyof design. Programmable options of the disclosed device are programmable by means of

both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulatingthe RC time constant behavior of word lines and digit lines during memory accesses, suchthat memory access cycle time can be optimized. Test data compression circuitryoptimizes the process of testing each cell in the array. On-chip topology circuitrysimplifies the testing of the device.

申请人：ONG; ADRIAN E,ZAGAR; PAUL S.,MANNING; TROY,KEETH; BRENT,WALLER;KEN

代理机构：Arnold, White & Durkee

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