VHDL 伪随机序列发生器
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发布时间：2022-04-25 00:02
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时间：2023-10-16 09:36
library ieee;
use ieee.std_logic_11.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PRSG is
port (reset,clk:in std_logic;
sel:in std_logic_vector(1 downto 0);
dout:out std_logic_vector(7 downto 0));
end PRSG;
architecture behavioral of PRSG is
signal ddout:std_logic_vector(7 downto 0);
signal temp:std_logic;
begin
process(sel)
begin
if reset='1' then
ddout<="00000000";
elsif clk'event and clk='1' then ------这里改下就行了
case sel is
when"00"=>ddout<="01010001";
when"01"=>ddout<="00110001";
when"10"=>ddout<="10001001";
when others=>ddout<="01111001";
end case;
temp<=ddout(0) xor ddout(3);
dout(0)<=ddout(1);
dout(1)<=ddout(2);
dout(2)<=ddout(3);
dout(3)<=ddout(4);
dout(4)<=ddout(5);
dout(5)<=ddout(6);
dout(6)<=ddout(7);
dout(7)<=ddout(7) xor temp;
end if;
end process;
end behavioral;
